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Monday, May 4, 2026

• Silicon-Proven 112Gbps SerDes IP Core in 12FFC Redefines High-Speed Connectivity with Unmatched Flexibility and Performance
• TES Electronic Solutions GmbH Provides a Configurable Display Controller IP for Flexible Embedded Video Applications
• Arteris (AIP) Is Up 20.7% After Expanded MIPS RISC-V Physical AI Partnership Has The Bull Case Changed?
• Surge in custom chip business propels VeriSilicon's Q1 revenue to double, with new orders skyrocketing to 8.2 billion yuan; increased R&D investment leads to wider net loss | Earnings Insight
• Cadence Reports First Quarter 2026 Financial Results
• QuickLogic Establishes New Banking Relationship and Secures $10 Million Revolving Credit Facility
• SkyeChip Berhad: Malaysia’s Leading IC Design & Silicon IP Company – Business Overview, Competitive Strengths & Future Plans
• "We Will Build a Korean Broadcom" ... Jaehong Park, CEO of BOS Semiconductors
• Satellite IoT connectivity: extending the IoT into Earth orbit
• AI Transforms the Chip Industry
• The great data center delay: Why your AI chips are stuck in 2026
• GUC Collaborate with Wiwynn to Advance Silicon-to-System Infrastructure for Next-Generation Hyperscale AI
• Arm AGI CPU Goes to Market via Supermicro and Verda at 2026 OCP EMEA Summit
• TSMC SoIC roadmap targets 2029 chip stacking

Thursday, April 30, 2026

• Arteris Wins Stevie Award for Technology Innovation of the Year
• Semifive Wins 3D IC Turnkey Design Deal for Edge AI Chip
• Korea Semiconductor Association Expands AI Innovation Center in Silicon Valley
• Siemens Industrial Edge ecosystem strengthens data and AI integration
• Microcontrollers for Machine Learning
• Tenstorrent Unveils Next-Gen Servers for Fast Tokens, No Disaggregation Needed
• Siemens fortifies cyber resilience to ensure energy supply for critical infrastructures
• A lunar network project powered by digital twins
• Auto China: Bosch pushes ahead with Level 3 highly automated driving​​​​​​​
• ISO 26262: The Impact of ASIL Metrics on Embedded Software Design
• Arteris, Inc. grows Poland engineering hub and strengthens European semiconductor ties
• Chip design firm SkyeChip sets Main Market IPO at 88 sen apiece to raise RM352 mil
• STMicroelectronics brings always-on vision to next-generation personal electronics with new ultralow-power image sensors
• Korea and Qatar to Expand Investment Cooperation in Manufacturing AI, Semiconductors, and Bio Industries
• Altair Semiconductor Secures $50M Funding Following Sony Spinoff to Accelerate IoT & 5G Innovation
• Vietnam, South Korea cooperate to develop semiconductor ecosystem, supply chain
• LTSCT Joins imec Automotive Chiplet Program
• Xylon Presents New 12-Channel GMSL3/GMSL2 FMC+ ExpansionBoard
• MIPI Alliance Launches Physical AI Birds of a Feather (BoF) Group Focused on Humanoids

Wednesday, April 29, 2026

• Perceptia Devices and Dolphin Semiconductor Partner to Deliver Best-in-Class IP Portfolio Covering Power Management, Clocking, High-Quality Audio and In-Situ Monitoring
• IC Manage Advances GDP-AI for Custom IC Design with Virtuoso

Tuesday, April 28, 2026

• TES is extending its PMU IP portfolio for X-FAB’s XT018 - 0.18µm BCD-on-SOI technology.

Monday, April 27, 2026

• Enabling the Chiplet Era: T2M Brings Production-Proven, UCIe-Ready Die-to-Die IP for Chiplet SOCs.
• CAST Introduces MAC-SEC-MG IP Core for Secure 10G+ Ethernet SoC Designs
• More Control, Less Chaos With Microchip’s New All-in-One DSCs
• Infineon joins European quantum pilot lines for quantum chips
• Ceva’s 5G NTN Modem IP Could Democratize Modems for Satellite Terminals
• Rambus Enables Power-Efficient AI Platforms with SOCAMM2 Server Module Chipset
• EU DARE Project Is Scrambling to Replace Codasip
• M31 Collaborates with TSMC to Achieve Tapeout of eUSB2V2 on N2P Process, Advancing Design IP Ecosystem
• Silvaco Partners with ITRI to Support MCU Development and Startup Innovation
• Atomera Extends Collaboration With Synopsys to Accelerate GaN Modeling in High-Value RF and Power Devices
• TSMC Latest Roadmap: A12, A13 for 2029 Without High-NA EUV; A16 Volume Production Delayed to 2027

Friday, April 24, 2026

• Arasan Announces immediate availability of its UFS 5.0 Host controller IP

Thursday, April 23, 2026

• EU unlocks €63M to accelerate AI in health and safety
• Crypto Quantique and Attopsemi Unite PUF and I-fuse® OTP technology to Deliver Zero-Overhead Device Enrollment on FinFET Technology
• LLMs in Transition: What Research, Real World Practice, and Europe Are Driving Forward Today
• Credo to Highlight Next-Generation Connectivity Solutions for AI Infrastructure at TSMC 2026 Technology Symposium
• Europe’s best-performing stock of 2026 rides AI photonics wave
• European Consortium Launches €50 Million SPINS Pilot Line to Industrialize Semiconductor Quantum Chips
• TSMC Q1 revenue tops $35.9bn on strong 3nm demand
• Wind River Joins the CHERI Alliance and Collaborates with Innovate UK to Accelerate Cybersecurity Innovation
• JEDEC® Previews LPDDR6 Roadmap Expanding LPDDR into Data Centers and Processing-in-Memory
• Cadence Collaborates with TSMC to Accelerate Design of Next-Generation AI Silicon
• Siemens collaborates with TSMC to advance AI for semiconductor design
• Synopsys Partners with TSMC to Power Next-Generation AI Systems with Silicon Proven IP and Certified EDA Flows
• TSMC Debuts A13 Technology at 2026 North America Technology Symposium
• Menta’s eFPGA Technology Adopted by AIST for Cryptography and Hardware Security Programs

Wednesday, April 22, 2026

• Silicon Creations Celebrates 20 Years of Global Growth and Leadership in 2nm IP Solutions
• GUC Announces 3nm 12 Gbps HBM4 PHY and Controller
• Arasan achieves the Industry’s First ASIL-D Certification for its CAN XL IP Core