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Saturday, March 1, 2025

• Does Your NPU Do VLMs? It Better!

Friday, February 28, 2025

• Guest Post: Current Challenges With Protecting Quantum Computing IP

Thursday, February 27, 2025

• Weebit Nano accelerates commercial activity through a licence with onsemi
• SEALSQ Enters Into Exclusive Negotiations to Acquire 100% of IC'ALPS
• Nvidia's Record $39.3 Billion Q1, Synopsys Q1 and Blackwell, Plus Chips Act Funding

Thursday, February 27, 2025

• Attopsemi Expands its Proven I-fuse® OTP Portfolio on X-FAB's 180nm Platform

Wednesday, February 26, 2025

• GlobalFoundries and MIT Collaborate to Advance Research and Innovation on Essential Chips for AI
• Ceva Unveils Latest High-Performance, High-Efficiency Communication DSPs for Advanced 5G and 6G Applications
• X-Silicon Revolutionizes AI and Graphics at the Edge with "Constellation" Software Platform
• Arm Drives Next-Generation Performance for IoT with World's First Armv9 Edge AI Platform
• SkyWater to Acquire Infineon's Austin Fab and Establish Strategic Partnership to Expand U.S. Foundry Capacity for Foundational Chips
• VeriSilicon unveils low-power AI Noise Reduction and AI Super Resolution IPs
• Dolphin Semiconductor Provides High-Performance LDO Regulators in TSMC 22nm to Ingenic for IPC Applications
• Attopsemi Expands its Proven I-fuse® OTP Portfolio on X-FAB's 180nm Platform
• Sustainable design is an evolution of industrial design

Tuesday, February 25, 2025

• Jim Keller joins ex-Intel chip designers in RISC-V startup focused on breakthrough CPUs
• Synopsys shares gain on stronger-than-expected earnings forecast
• Interview with Xiphera CEO - Adapting to Market Changes
• PsiQuantum Announces Omega, a Manufacturable Photonic Quantum Computing Chipset
• Socionext Announces Strategic Partnership with Google Quantum AI in Quantum Computing Development
• QuickLogic Announces $1.1M eFPGA IP Contract with new Defense Industrial Base Customer
• Intel, Synopsys, TSMC All Unveil Record Memory Densities The move to nanosheet transistors is a boon for SRAM
• Meet T2M @ MWC 2025 to learn about Cutting-Edge RF, Wireless, Automotive Semiconductor IP Cores & ASIC services
• BrainChip Collaborates with Onsor Technologies To Power Epileptic Seizure-Detecting Glasses
• Semiconductor Industry Faces a Seismic Shift
• Baya Systems and Semidynamics Collaborate to Accelerate RISC-V System-on-Chip Development

Monday, February 24, 2025

• Dnotitia and Finders Establish Strategic Partnership to Develop AI-driven Insurance Solution
• Andes Technology and proteanTecs Partner to Bring Performance and Reliability Monitoring to RISC-V Cores
• Arteris Releases the Latest Generation of Magillem Registers to Automate Semiconductor Hardware/Software Integration
• Imagination takes efficiency up a level with latest D-Series GPU IP
• Q.ANT and IMS CHIPS Launch Production of High-Performance AI Chips, Establish Blueprint for Strengthening Chip Sovereignty
• sureCore PowerMiser IP enables KU Leuven chip for AI applications to achieve dynamic power saving of greater than 40%

Sunday, February 23, 2025

• TSMC's Efforts In 2nm Production Could See The Company Reaching 50,000 Monthly Wafers In 2025; With Both Facilities Operational, Output Could Reach 80,000 Units
• Maximum efficiency at minimum power consumption: New options for integrating RFicient® receivers
• Intel set to begin 18A tape-outs later this year, according to reports
• Cortus MINERVA Out-of-Order 4GHz 64-bit RISC-V Processor Platform targets automotive applications
• Quadric Announces Lee Vick is New VP Worldwide Sales
• ZeroPoint Technologies Unveils Groundbreaking Compression Solution to Increase Foundational Model Addressable Memory by 50%
• AheadComputing Raises $21.5M Seed Round and Introduces Breakthrough Microprocessor Architecture Designed for Next Era of General-Purpose Computing
• Siemens delivers certified and automated design flows for TSMC 3DFabric technologies

Friday, February 21, 2025

• Veriest Solutions Strengthens North American Presence at DVCon US 2025

Thursday, February 20, 2025

• Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification

Thursday, February 20, 2025

• STMicroelectronics to ramp new silicon photonics process

Wednesday, February 19, 2025

• STMicroelectronics Unveils Silicon Photonics, BiCMOS Technologies to Power Next-Gen AI Data Centers
• Ex-Intel team raise $21.5m to pursue RISC-V for AI
• Driving the efficiency of artificial intelligence
• EU funding for Infineon Dresden smart power fab approved
• Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
• Intel in advanced talks to sell Altera to Silverlake
• CEA and Quobly Report Simultaneous, Microsecond Qubit-Readout Solution With 10x Power-Use Reduction
• CEA and Quobly Report Simultaneous, Microsecond Qubit-Readout Solution With 10x Power-Use Reduction

Wednesday, February 19, 2025

• 2025 Outlook with Paul Wells of sureCore

Tuesday, February 18, 2025

• Getting Started with Chip Eco-Design Methodology
• YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
• CEA and Quobly report microsecond qubit-readout solution with 10x power-use reduction
• RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
• Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results

Monday, February 17, 2025

• €29m for 6G chiplet packaging line in Finland
• VeriSilicon: The "IP family" is on fire, and the three major markets will go hand in hand in 2025
• Synopsys Teams Up with SEMI Foundation to Drive Workforce Development Initiatives in Semiconductor Industry
• Unlocking Quantum Advantage Lies Not Just with Qubits but with Gates
• S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
• AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
• AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset