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Thursday, August 4, 2022

• Intel tGPU Setback Expected to Slow TSMC's 3 nm Ramp
• Nordic Semi sets up RISC-V design team
• Brite Semiconductor provides xSPI/Hyperbusâ„¢/Xcellaâ„¢ controller and PHY total solution
• Brite Semiconductor provides xSPI/Hyperbus™/Xcella™ controller and PHY total solution
• GUC Monthly Sales Report - July 2022
• Cadence Accelerates Hyperscale SoC Design with Industry's First Verification IP and System VIP for CXL 3.0

Wednesday, August 3, 2022

• STMicroelectronics Supports the World Transitions to Digitalization and Decarbonization with its Pioneered FD-SOI Technology
• Neuromorphic Device with Low Power Consumption
• Edge Impulse Releases Deployment Support for BrainChip Akida Neuromorphic IP
• Rambus Reports Second Quarter 2022 Financial Results
• Architect of CHIPS Act Speaks on Its Impact
• Efinix® Extends Breakthrough Family of Titanium Products with Launch of the Titanium Ti180 FPGA
• June Swoon - IC Sales Turn Negative as Economy Weighs on Market
• UMC Reports Sales for July 2022
• Intel Orders Delayed, TSMC Slows Three-Nanometer Expansion, Says TrendForce
• IPrium releases CCSDS TC Telecommand LDPC Encoder and Decoder
• Access Advance VVC Patent Pool Momentum Grows
• Cadence Library Characterization Solution Accelerates Delivery and Enhances Quality of Arm Memory Products

Tuesday, August 2, 2022

• UCIeâ„¢ (Universal Chiplet Interconnect Expressâ„¢) Consortium Announces Incorporation and New Board Members; Open for Membership
• UCIe™ (Universal Chiplet Interconnect Express™) Consortium Announces Incorporation and New Board Members; Open for Membership
• CXL Consortium Releases Compute Express Link 3.0 Specification to Expand Fabric Capabilities and Management
• Global Semiconductor Sales Increase 13.3% in Q2 2022 Compared to Q2 2021
• Imperas leads the RISC-V verification ecosystem as the first to release an open-source SystemVerilog RISC-V processor functional coverage library
• Alma Technologies Announces the Immediate Availability of an Ultra-High Throughput Image Scaler IP Core
• Accellera Announces Proposed Working Group to Explore Clock Domain Crossing Standard

Monday, August 1, 2022

• Soitec: Paul Boudre Hands Over CEO Role to Pierre Barnabé
• Mobiveil and Avery Design Systems Extend Partnership to Accelerate Design and Verification of NVMe 2.0-Enabled SSD Development
• Avery Announces 800G Ethernet VIP virtual network co-simulation platform, enabling SoC pre-silicon validation in real networked application environments
• OPENEDGES Passes the Eligibility Examination of the KOSDAQ listing
• NSITEXE expands products lineup of RISC-V CPU supported functional safety
• Rambus Appoints Desmond Lynch as Chief Financial Officer
• CXL Consortium and OpenCAPI Consortium Sign Letter of Intent to Transfer OpenCAPI Specifications to CXL
• Avery Design Announces CXL 3.0 VIP
• PUFsecurity gains Riscure accreditation for its Anti-Tamper solution, PUFrt

Sunday, July 31, 2022

• Open source chip programme expands to 90nm FDSOI
• Avery Design Systems Verification IP Helps Solid State Storage Controller Startup Validate its Designs and Get to Market Faster
• U.S. Passes CHIPS Act, Increasing Restrictions on China Lead to Rising Geopolitical Risk, Says Trendforce
• SD/eMMC Host and Device Controller IP Cores including matching PHYs with high performance, and high storage capacity available for license to secure your removable and embedded storage

Wednesday, July 27, 2022

• SkyWater Receives Funding from DOD, Partners with Google to Facilitate Open Source Design for its new 90 nm Technology Offering
• NSITEXE product brand "Akaria", expand portfolio
• Faraday Reports Second Quarter 2022 Results
• Worldwide Silicon Wafer Shipments Set New Record in Q2 2022, SEMI Reports
• Arm announces appointment of Spencer Collins as Chief Legal Officer
• Renesas Announces Consolidated Forecasts
• Faraday Unveiled FPGA-Go-ASIC Prototyping Platform to Accelerate FPGA-to-ASIC Conversion

Tuesday, July 26, 2022

• Gartner Forecasts Worldwide Semiconductor Revenue Growth to Slow to 7% in 2022
• MIPI UniPro v2.0 Doubles Peak Data Rate and Delivers Greater Throughput and Reduced Latency for Flash Memory Storage Applications
• Xfuse, LLC Enters AI Vision Market with New Image Signal Processing (ISP) Technology

Monday, July 25, 2022

• EnSilica turns to QLS to strengthen sales networks in North America
• Intel to manufacture MediaTek Edge chips, instead of TSMC
• Samsung Foundry Achieves 2X Productivity on Large-Scale Analog and Mixed-Signal IP with the Spectre FX Simulator
• DCD-SEMI adds extra features to LIN IP Core and GuardKnox license the solution

Monday, July 25, 2022

• Alma Technologies Scales-up the Performance of the JPEG-LS Image Compression IP Core by Employing its Ultra High Throughput - UHTâ„¢ Architecture

Sunday, July 24, 2022

• History is made! Samsung beats out TSMC and starts shipping 3nm GAA chipsets
• Intel and MediaTek Form Foundry Partnership
• Cadence Expands into Molecular Simulation with Acquisition of OpenEye Scientific, a Pioneering Leader in Computational Molecular Design
• eMMC Holds Its Own Against UFS
• SMIC shipping 7nm ICs
• CIX Technology joins Linaro's Windows on Arm Group
• 5G Sub-6GHz RF Transceiver IP Cores, available for immediate licensing to the customers for Cellular and Industrial IoT applications
• CAES' Quad Core LEON4FT Processor Selected for Next-Generation On-orbit Servicing Spacecraft
• Silicon Labs Selects CoreHW Advanced Bluetooth AoA Switch for Dual Polarized Antenna Array Pro Kit
• Creonic Offers High-throughput Single-chip DVB-S2X Satellite Modem for Zynq UltraScale+ RFSoC
• CFX announces commercial availability of anti-fuse OTP technology on 55nm CIS process

Saturday, July 23, 2022

• Wi-Fi Alliance® claims Wi-Fi® delivers strong IoT advantage