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Sunday, June 19, 2022

• Silicon Topology Joins TSMC Design Center Alliance (DCA)
• VisualSim Antenna System Designer enables simulation of Antenna and Communication Systems
• World's first end-to-end integration of ZKP with FPGAs.
• Fraunhofer IPMS develops CANsec Controller IP-Core CAN-SEC
• Huawei and Nordic cellular IoT licensing deal takes a big step towards industry-wide component-level licensing
• World's First AV1 Decoder Silicon IP with support for 12-bit pixel size and 4:4:4 Chroma Sub-Sampling Released by Allegro DVT
• Complete UFS 3.1 Controller solution (Analog / Digital IP Cores) licensed to China's leading Smartphone Company
• Samsung Ventures invests in Israeli AI systems and semiconductor company NeuReality

Thursday, June 16, 2022

• Embedded World fair: Menta will unveil an unprecedented collaboration with Everspin Technologies
• TSMC FINFLEX™, N2 Process Innovations Debut at 2022 North American Technology Symposium
• Cadence RFIC Solutions Support TSMC N6RF Design Reference Flow
• Synopsys Boosts 5G SoC Development Productivity with New RF Design Flow for TSMC N6RF Process

Wednesday, June 15, 2022

• Siemens extends support of multiple IC design solutions for TSMC's latest processes
• Avery Design Systems Announces Verification Support for New UCIe standard, Accelerating Adoption of Chiplet Interconnect Protocol
• QuickLogic and eTopus Announce Disaggregated, Flexible eFPGA Chiplet Template
• OpenFive Joins Universal Chiplet Interconnect Express (UCIe) Consortium
• Alchip Technologies Offers 3nm ASIC Design Services
• Renesas Develops Circuit Technologies for 22-nm Embedded STT-MRAM with Faster Read and Write Performance for MCUs in IoT Applications
• Cadence Design IP portfolio in TSMC's N5 Process Gains Broad Adoption Among Leading Semiconductor and System Companies
• CAST and Fraunhofer IPMS Mark 20-Year Partnership with Product of the Year Win
• SmartDV Charts Course Toward Chiplets, Joins Universal Chiplet Interconnect Express (UCIe)

Tuesday, June 14, 2022

• ST looks at joint European wafer fab with GlobalFoundries
• Renesas Launches Cellular-to-Cloud IoT Development Platforms Powered by RA and RX MCU Families
• Finwave targeting 5G with 3DGaN FinFET technology
• Japan targeting 2025-7 for 2nm process
• Think Silicon to Unveil Industry's First RISC-V 3D GPU at Embedded World 2022
• Veriest expands Embedded Software team to provide full engineering services
• The Five Biggest MCU Suppliers Accounted for 82% of 2021 Sales

Monday, June 13, 2022

• GaN Systems & TSMC Showcase Latest Power Electronics Advances at 2022 TSMC Technology Symposium
• Imagination GPU approved by HORIBA MIRA Certification Limited for functionally safe ADAS and HMI applications
• Allegro DVT Acquires Labwise Ltd. to Extend its Compliance Stream Business Line and Enrich its Products & Service Portfolio
• Real Intent Advances Meridian CDC with Multimode Coverage & Unprecedented 10X Efficiency
• Intrinsic ID Signs Representation Agreement with Kaviaz Technology to Extend the Commercial Reach of its Physical Unclonable Function (PUF) Security IP Solutions in Taiwan
• Renesas Announces Investment in Popular Open-Source Company Arduino to Access Huge Developer Community
• Codasip appoints Mike Eftimakis as VP of Strategy and Ecosystem
• intoPIX takes part in Major VSF Interoperability Demonstrations at VidTrans 2022

Sunday, June 12, 2022

• BrainChip, Edge Impulse Team to Develop Low-Cost Embedded ML Systems
• Global Fab Equipment Spending Expected to Reach Record $109 Billion in 2022, SEMI Reports
• Cadence Extends Cloud Leadership with Transformational Cadence OnCloud SaaS and e-Commerce Platform
• Altair Expands Electronic System Design Technology with Acquisition of Concept Engineering
• IAR Systems accelerates innovation for solutions based on Arm Cortex-M85 processor
• Synopsys Drives Chip Innovation for Next-Generation Mobile and HPC Designs on TSMC N3E and N4P Processes
• Cadence Digital and Custom/Analog Design Flows Certified by TSMC for Latest N3E and N4P Processes
• SkyWater Announces Availability of SRAM Memory Compiler for 90 nm Strategic Rad Hard by Process Offering
• Wi-Fi 6 (AX)/BLE/15.4 22nm Combo RF IP Core, Licensed to a leading Chinese Semiconductor Company for IoT Chipset
• Alphawave IP Announces Availability of Two New Interconnect IP Products in TSMC Advanced Processes
• Analog Bits to Demonstrate Pinless PLL and Sensor IP's in TSMC N5 Process at TSMC 2022 North America Technology Symposium
• TSMC May 2022 Revenue Report

Thursday, June 9, 2022

• SkyWater adds FDSOI SRAM IP
• Mosaid Announces Semiconductor Process License Agreement
• Cadence Cerebrus AI-Based Solution Delivers Transformative Results on Next-Generation Customer Designs
• Mosaid Acquires Major Semiconductor Process Portfolio
• Mark Potter and Christian Klingler Join proteanTecs Advisory Board
• CAES announces Space Grade Qualification of Quad Core LEON4FT Microprocessor

Wednesday, June 8, 2022

• Cadence Revolutionizes System Design with Optimality Explorer for AI-Driven Optimization of Electronic Systems
• Cadence Extends Cloud Leadership with Transformational Cadence OnCloud SaaS and e‑Commerce Platform
• World's Top Ten IC Design Company Revenue Reached US$39.43 billion in 1Q22, Marvell Growth Rate Tops List, Says TrendForce
• OIF Releases Common Electrical I/O 5.0 Implementation Agreement
• BSC and Intel announce a joint laboratory for the development of future zettascale supercomputers
• Toshiba and Japan Semiconductor Develop Highly Reliable Versatile Analog Platform with Floadia's G1 technology for Automotive Applications
• Texas Instruments Keeps A Firm Grip As World's Top Analog IC Supplier
• TEMPO AI chip tapes out with videantis processor platform
• Soitec reports full year results of fiscal year 2022
• CEVA Expands Sensor Fusion Product Line with New Sensor Hub MCU for High Precision Motion Tracking and Orientation Detection
• Renesas to Acquire Reality AI to Bring Advanced Signal Processing and Intelligence to the Endpoint
• Fraunhofer IPMS RISC-V processor core supported by debugging tool from Lauterbach
• First RISC-V-Based System-on-Chip (SoC) FPGA Enters Mass Production

Tuesday, June 7, 2022

• €140m 3D chip research centre opens in Dresden
• CEVA Bluetooth® 5.3 Platform IP Supports New Auracastâ„¢ Broadcast Audio, Transforming the Shared Audio Experience
• CEVA Bluetooth® 5.3 Platform IP Supports New Auracast™ Broadcast Audio, Transforming the Shared Audio Experience
• QuantWare awarded €7.5M from the European Innovation Council to rapidly scale superconducting quantum processors
• QuantWare awarded €7.5M from the European Innovation Council to rapidly scale superconducting quantum processors
• Agile Analog signs first Chinese licensee for its analog IP
• Arm introduces new image signal processor to advance vision systems for IoT and embedded markets
• Intrinsic ID Announces Embedded SRAM PUF Security IP for Military-Grade IP protection in Intel FPGAs
• Spectronite introduces a high-performance 5G wireless solution for mobile operators
• The Automotive Industry is driving down acceptable chip defect levels
• Agile Analog signs first Chinese licensee for its analog IP
• 14-bit, 4.32Gsps Ultra high speed Wideband, Time-Interleaved Pipeline ADC IP Cores available for license to customers for wide range of applications