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Sunday, March 13, 2022

• Grenoble INP - Phelma, UGA and Soitec sign their first partnership agreement
• New process to help tech firms develop safer AI
• Russia and The 5G Cold War
• SEGGER announces that Renesas has licensed emWin for all RX microcontrollers
• HDMI 2.0 Tx PHY in 12FFC along with Controller IP Core with high lossless Audio/Video data transfer, licensed for a 4KTV SoC
• Rambus Announces James Mitarotonda to Become Board Advisor
• IAR Systems extends powerful RISC-V solutions with 64-bit support
• Codasip University Program spurs innovation and boosts curriculums
• Alphawave IP Announces Definitive Agreement to Acquire Entire OpenFive Business Unit from SiFive for US$210m in cash

Thursday, March 10, 2022

• China's foundry growth to remain slow for next 5 years

Wednesday, March 9, 2022

• Imagination and Realtek launch world-first image compression DTV SoC
• QuickLogic Announces a New Approximately $1M eFPGA Contract
• AlphaICs welcomes IEEE Fellow Michael Shebanow as Chief Technology Officer
• PragmatIC Semiconductor leads project to digitise reusable packaging
• QuantWare releases 25-qubit Contralto QPU
• Zepp Health signs licence agreement for sureCore's EverOn ultra-low voltage memory IP
• TSMC February 2022 Revenue Report
• OPENEDGES Announces Silicon Proven 12nm LPDDR54 PHY IP
• Rambus Accelerates Automotive SoC Design with ASIL-B Certified Embedded Hardware Security Module
• SEGGER collaborates with HPMicro making Embedded Studio for RISC-V available at no cost
• GUC Announces 2.5D and 3D Multi-Die APT Platform for AI, HPC, Networking ASICs

Tuesday, March 8, 2022

• The Future of Automotive Connectivity
• Securing the Future with Trusted Traceability and Blockchain
• 2022 to Mark the Third Year in a Row of ≥20% Growth for the Foundry Market
• 2022 to Mark the Third Year in a Row of ≥20% Growth for the Foundry Market
• UK startup is raising funds for Open Power processor
• Arasan announces the immediate availability of its MIPI D-PHY IP as Tx Only or Rx Only for the GlobalFoundries 12nm FinFET process node
• Ubiscale announces new customer for Cobalt, its low-power GNSS IP core

Monday, March 7, 2022

• Semiconductor Sales Up 27% in January
• Secure-IC in the FT 1000: the sixth annual list of EuropeÂ’s fastest-growing companies
• Next-gen edge AI accelerator SoC in development
• Vidatronic Announces the 5nm FinFET Power Management IP Series for Ultra-Low-Power, System-on-a-Chip (SoC) Integration
• Reshoring Chip Industry Risks Failure With Just More Fabs
• Andes Technology Announces over 10 Billion Cumulative Shipments of Andes-Embedded SoCs and Records All-Time High Annual and Monthly Revenue in 2021
• QuickLogic Announces First Rad-Hard eFPGA IP for SkyWater RH90 Process

Sunday, March 6, 2022

• Renesas expands options with Andes-based RISC-V MPU
• GlobalFoundries Announces Next-Gen Silicon Photonics Solutions
• GlobalFoundries Announces Next Generation in Silicon Photonics Solutions and Collaborates with Industry Leaders to Advance a New Era of More in the Data Center
• Synopsys Extends OptoCompiler Support for New GF Fotonix Platform
• ZeroPoint Technologies signs Memory Encryption contract
• GUC Monthly Sales Report - February 2022
• Flex Logix and the Air Force Research Laboratory Expand their License to Include any Flex Logix Technology for Research and Chip Prototyping in all Available Processes including Radhard
• Ambient Scientific Announces Beta Release of Software Compilers for its Programmable AI Processor GPX-10
• OpenFive and EdgeCortix Collaborate on an AI Accelerator Custom SoC
• sureCore appoints Taiwan Dream Services Company to spearhead its growth into the APAC wearables market
• PCIe 5.0 SerDes PHY and Controller IP Cores for all High-End Serial connect Interfaces in advanced SoCs is available for immediate licensing

Friday, March 4, 2022

• TSMC's enhanced 3nm process node (N3e) to start production a quarter ahead of schedule

Thursday, March 3, 2022

• TSMC joins Intel-led chiplet alliance as founding member
• Agile Analog's Approach to Analog IP Design and Quality — Why "Silicon Proven" is NOT What You Think
• Credo Expands High Performance Seagull Family With Integrated 50Gbps PAM4 VCSEL and EML Drivers
• Arteris Announces Financial Results for the Fourth Quarter and Full Year 2021 and Estimated First Quarter and Full Year 2022 Guidance
• UMC Reports Sales for February 2022
• Global Semiconductor Sales Increase 26.8% Year-to-Year in January

Wednesday, March 2, 2022

• Open standard for RISC-V verification is announced at DVCon
• Graphcore Supercharges IPU with Wafer-on-Wafer
• Codasip steps up its focus on Europe and appoints Till-Vattier as EMEA VP
• oneNav Announces pureL5 GNSS Digital IP Core and Customer Evaluation System - World's First Single Frequency L5 GNSS Receiver
• Leaders in Semiconductors, Packaging, IP Suppliers, Foundries, and Cloud Service Providers Join Forces to Standardize Chiplet Ecosystem
• Microsoft Executive Bobby Yerramilli-Rao Joins GlobalFoundries Board of Directors
• Dolphin Design chooses DEFACTO's SoC Compiler 9.0: a turnkey methodology to reduce project costs and increase team efficiency
• Dolphin Design chooses DEFACTO's SoC Compiler 9.0: a turnkey methodology to reduce project costs and increase team efficiency

Tuesday, March 1, 2022

• How to Mitigate IoT Security Threats in 2022
• CEA and Spectronite develop software radio for spectrally efficient backhaul solutions
• RISC-V AI Chips Are Joining GPU Race for AI Processing
• Small Prime Divisors Attack and Countermeasure against the RSA-OTP Algorithm
• Pankaj Mayor Joins Arteris IP as Executive Vice President of Global Sales
• Khronos Releases Vulkan SC 1.0 Open Standard for Safety-Critical Accelerated Graphics and Compute
• Sondrel explains the 10 steps to model and design a complex SoC
• Semi Industry Capex Forecast to Jump 24% and Reach Over $190 Billion This Year
• Cadence Recognized with TSMC OIP Ecosystem Forum Customers' Choice Award for 3D-IC Design
• Imperas unifies new RISC-V verification ecosystem with RVVI