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Tuesday, September 23, 2025

• Nordic Semiconductor launches full device observability and OTA capabilities via nRF Cloud powered by Memfault
• New Investments Flowing Into Photonics
• Thalia and X-FAB Forge Strategic Partnership to Safeguard Supply and Accelerate IP Migration
• Siemens accelerates complex semiconductor design and test with Tessent IJTAG Pro
• EnSilica and Codasip announce strategic partnership
• MIPI A-PHY Reaches Milestone of First SerDes Standard to Enter Mass Production with Global Automotive OEM

Monday, September 22, 2025

• TSMC 2nm Customer Surge: 15 Clients Reportedly Secured, 10 in HPC
• OpenAI and NVIDIA Announce Strategic Partnership
• NanoEdge AI Studio v5, 1st AutoML tool with Synthetic Data Generation
• Analog Bits Adds New Power and Energy Management IP Blocks Proven on TSMC N2P and N3P Processes at TSMC 2025 OIP Ecosystem Forum

Sunday, September 21, 2025

• BOS CEO, Jaehong Park, Introduces Eagle-N - Our Innovative AI Accelerator

Friday, September 19, 2025

• STMicroelectronics and the Transformation of the Automotive Industry
• 22nm RISC-V AI Chip Targets Wearables and IoT

Thursday, September 18, 2025

• Deca, SST collaborate on NVM chiplet solutions
• Making connections: The pursuit of chiplet interconnect standardization
• Nvidia takes $5bn stake in Intel, becoming one of the company’s biggest shareholders
• EPI Forum in Paris, October 6-7, L'Hotel des Arts & Metiers
• Nordic Semiconductor expands the nRF54L Series with nRF54LM20A, a high-memory wireless SoC for advanced Bluetooth LE and Matter applications
• Silicon Creations Announces 1000th Production FinFET Tapeout at TSMC and Immediate Availability of Full IP Library on TSMC N2 Technology
• Comcores MACsec IP is compliant with the OPEN Alliance Standard
• RISC-V: Shaping the Future of Mobility with Open Standards and Strong Partnership
• Ceva Appoints Former Microsoft AI and Hardware Leader Yaron Galitzky to Accelerate Ceva's AI Strategy and Innovation at the Smart Edge
• Sofics joins GlobalFoundries' GlobalSolutions Ecosystem to Enhance Chip Robustness, Performance and Design Efficiency
• Qualitas Semiconductor Successfully Demonstrates Live UCIe PHY IP at AI Infra Summit 2025

Wednesday, September 17, 2025

• Why Chip Legend Jim Keller and Tenstorrent Are Betting on Taiwan
• Room-Temperature Quantum Can Revitalize Europe's Semiconductor Industry
• TSMC's SiC Substrate Strategy: Scaling Thermal Performance for AI and 3D Packaging
• Omni Design Technologies Secures over $35 Million in Series A Funding to Advance Its Leadership in Wideband Signal Processing™ for the AI Data Revolution
• Dnotitia Unveils VDPU IP, the First Accelerator IP for Vector Database
• Qualitas Semiconductor Signs PCIe Gen 4.0 PHY IP License Agreement with Leading Chinese Fabless Customer

Tuesday, September 16, 2025

• ARTE Debuts New MPEG-H Dialog+ Feature
• Analog Power Conversion LLC adopts Silvaco’s Design Technology Co-Optimization Flow for Next Generation Silicon and Silicon Carbide Power Devices
• Siemens unveils groundbreaking Tessent AnalogTest software for automated analog circuit test generation
• STMicroelectronics to advance next-generation chip manufacturing technology with new PLP pilot line in Tours, France
• Canadian AI company Cohere opens Paris hub to expand EMEA operations
• Cadence Collaborates with NVIDIA to Predict Data Center Power Demands
• Putting 3D IC to work for you
• MediaTek's First Chipset Using TSMC's 2nm Process Expected in Late 2026
• TSMC's first 2 nm Node Customers are Apple, AMD, NVIDIA, and MediaTek; Intel Missing

Monday, September 15, 2025

• Keysight to Demonstrate New Solutions that Support AI Infrastructure and Optical Innovations at ECOC 2025
• Altera CEO: 'We Need To Fully Focus On Execution'
• Infineon Reportedly Set to Build RISC-V Auto MCUs at TSMC Dresden Fab, Mass Production in 2028
• MCU Design Enablement: T2M-IP Expands Footprint via Key IP Licensing in South Korea
• SK hynix Maintains Memory Leadership with First HBM4
• Leading UK semiconductor firm up for sale
• Europe's Semiconductor Plan Caught Between Vision and Reality
• AccelerComm Joins the Mobile Satellite Services Association (MSSA)
• Qualcomm and Valeo join hands to provide pre-integrated ADAS & AD platform
• BOS CSO Highlights Future of Automotive AI at AI Semiconductor Forum
• Axelera AI Boosts LLMs at the edge by 2x with the Metis M.2 Max
• RISC-V IP expands AI capabilities at the edge
• Arm Goes for Rebrand for Mobile CSS, Drops Cortex, Immortalis
• Socionext and imec Update Core Partner Program
• Intel Announces Key Leadership Appointments to Accelerate Innovation and Strengthen Execution
• From Foundry to Forum: Taiwan's Repositioning in the New Semiconductor Order
• Silicon Photonics in the Spotlight: TSMC Lifts the Curtain on COUPE at SEMICON Taiwan
• TSMC Moves to Lead in "Silicon Photonics"... More Than Twice as Many Patent Applications as Intel
• Dnotitia's "Seahorse Cloud 2.0" Ushers in a New Era of Enterprise AI with "AgentOps"

Sunday, September 14, 2025

• Korea tackles quantum 'harvest now, decrypt later' threat

Thursday, September 11, 2025

• Samsung’s Exynos 2600 Beats Apple's A19 Pro in Shocking Benchmark Upset
• Alibaba, Baidu begin using own chips to train AI models, The Information reports
• Auracast broadcast audio solution powers assistive listening in public spaces with Nordic Semiconductor wireless connectivity
• Valens Semiconductor and Samsung partner to enhance the MIPI A-PHY standard
• ASML, Mistral AI enter strategic partnership
• SiFive's New RISC-V IP Combines Scalar, Vector and Matrix Compute to Accelerate AI from the Far Edge IoT to the Data Center
• IntoPIX JPEG XS Powers Barnfind BarnPalette Flow-XS For Next-Generation Broadcast Workflows
• Deca and Silicon Storage Technology Announce Strategic Collaboration to Enable NVM Chiplet Solutions
• Perceptia Begins Port of pPLL03 to Samsung 8nm Process Technology