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Tuesday, May 20, 2025

• GlobalFoundries partners with A*STAR to accelerate advanced packaging innovation
• Steering the future: advanced satellite communications phased arrays with GF 45RFSOI, 45RFE and 130NSX
• Infineon to revolutionize power delivery architecture for future AI server racks with NVIDIA
• Movellus Claims First On-Die Power Delivery Network Analyzer
• Advanced IC Packaging: The Roadmap to 3D IC Semiconductor Scaling
• sureCore extends its sureFIT design service to include custom memory solutions for AI applications
• NVIDIA Unveils NVLink Fusion for Industry to Build Semi-Custom AI Infrastructure With NVIDIA Partner Ecosystem

Monday, May 19, 2025

• Six HCLTech campuses in India receive the coveted TRUE Zero Waste Platinum Certification
• Programmable AI Silicon Would Help Meet AI Workload Demand
• Siemens to bring advanced timing constraint capabilities to EDA design flow with Excellicon acquisition
• RISC-V Technology Seeing Growing Maturity and Penetration
• Secure-IC at Computex 2025: Enabling Trust in AI, Chiplets, and Quantum-Ready Systems
• InPsytech Joins Samsung SAFE™ IP Partner Program for Excellence in ONFI and UCIe IP Solutions
• Semidynamics: From RISC-V with AI to AI with RISC-V
• Codasip: Toward Custom, Safe, Secure RISC-V Compute Cores
• Versatile Whitebox 1G Ethernet PHY IP Core with BroadR-Reach™ for Connected Automotive and Industrial Systems

Sunday, May 18, 2025

• Imec and TNO Launch Holst Centre Photonics Lab to Accelerate Integrated Photonics Innovation in the Netherlands

Friday, May 16, 2025

• Sustainable supply chain: training for Leonardo's suppliers
• Samsung Reportedly Revises High-NA EUV Plans: Limited Memory Use, Foundry Begins at 1.4nm
• Automotive Industry Charts New Course with RISC-V
• Quantum Computing Roadmaps: A Look at The Maps And Predictions of Major Quantum Players
• Arm Evolves Compute Platform Naming for the AI Era
• TSMC Board of Directors Meeting Resolutions
• Semidynamics: From RISC-V with AI to AI with RISC-V
• Perforce Partners with Siemens for Software-Defined, AI-Powered, Silicon-Enabled Design

Thursday, May 15, 2025

• Putting UCIe in Context
• Keysight Quantum Control System Embedded within Fujitsu and RIKEN’s World-Leading 256-Qubit Quantum Computer
• Canada's Chip Industry Charts Best Path to Growth
• Perforce Partners with Siemens for Software-Defined, AI-Powered, Silicon-Enabled Design
• Arteris Announces Financial Results for the First Quarter and Estimated Second Quarter and Updated Full Year 2025 Guidance
• Secafy Licenses Menta's eFPGA IP to Power Chiplet-Based Secure Semiconductor Designs

Wednesday, May 14, 2025

• Parallel AI RISC-V compiler enters alpha testing
• Synopsys ramps up collaboration with Taiwan's TSMC on A16 process
• 5G-OT Alliance launched to bring 5G/LTE to OT environments
• Rambus Delivers Industry-Leading Client Chipsets for Next-Generation AI PC Memory Modules
• Siemens leverages AI to close industry's IC verification productivity gap in new Questa One smart verification solution

Tuesday, May 13, 2025

• ComputeRAM in AI accelerators: An LLM case study
• TSMC Board of Directors Meeting Resolutions
• Renesas Partners with Indian Government to Drive Innovation Through Startups and Industry-Academia Collaboration, Strengthening India’s Semiconductor Ecosystem
• QuickLogic Reports Fiscal First Quarter 2025 Financial Results
• Historic Quantum Technology Agreement Signed by EU, Japan
• Arteris Q1 2025 presentation highlights 28% revenue growth, strategic automotive wins
• Alps Alpine Adopts Silvaco's Jivaro Pro to Accelerate SPICE Post-Layout Simulation
• SMIC Q2 revenues to take 6% hit due to tool maintenance and validation issues
• Andes Technology Showcases RISC-V AI Leadership at RISC-V Summit Europe 2025
• See the 2025 Best Edge AI Processor IP at the Embedded Vision Summit
• RISC-V International Promotes Andrea Gallo to CEO

Monday, May 12, 2025

• UK takeover panel gives Qualcomm till May 27 to make a bid for Alphawave
• Samsung's 12nm-class Automotive LPDDR5X: DRAM for safety-critical centralized automotive systems
• RISC-V Royalty-Driven Revenue to Exceed License Revenue by 2027
• Cadence Unveils Millennium M2000 Supercomputer with NVIDIA Blackwell Systems to Transform AI-Driven Silicon, Systems and Drug Design
• Keysom Unveils Keysom Core Explorer V1.0
• Ceva, Inc. Announces First Quarter 2025 Financial Results

Friday, May 9, 2025

• Meet DCD-SEMI at GITEX Europe 2025 — and RnD Con 2025!
• KEYSOM is heading to RISC-V Summit Europe in Paris!
• VESA Releases Compliance Test Specification Model for DisplayPort Automotive Extensions Standard
• Imagination Announces E-Series: A New Era of On-Device AI and Graphics
• SiFive and Kinara Partner to Offer Bare Metal Access to RISC-V Vector Processors
• PQSecure Partners with Menta SAS to Demonstrate Leakage-Resistant PQC IPs on eFPGA Fabric

Thursday, May 8, 2025

• The future of AI runs on the GPU
• $50m quantum computing lab for Paris
• Tensilica AI co-processor for automotive
• Cadence and AVCC to Advance Physical AI Innovations for Autonomous Vehicles
• Xylon at ADAS&AVT Expo Europe 2025
• Xylon Introduces Xylon ISP Studio
• Kyocera Licenses Quadric's Chimera GPNPU AI Processor IP
• Axiomise Featured Gold Sponsor at RISC-V Summit Europe Next Week in Paris
• Cadence Accelerates Physical AI Applications with Tensilica NeuroEdge 130 AI Co-Processor