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Wednesday, February 18, 2026

• Keysight Introduces PAM3 Signaling with New GDDR7 Transmitter Compliance Solution for Next-Generation Graphics Memory
• Keysight Unveils 3D Interconnect Designer for Chiplet and 3DIC Advanced Package Designs

Monday, February 16, 2026

• TES Launches its µEngine: Parallel CPU System for Deterministic Real-Time HDL Applications
• DVB-S2 Modulator Available For Implementation From Global IP Core
• Semiconductor sales set new record as logic and memory lead growth
• EnSilica to highlight turnkey ASIC expertise and European supply resilience at embedded world 2026
• Victor Peng Joins Rambus Board of Directors
• Fraunhofer IPMS develops new 10G TSN endpoint IP Core for deterministic high-speed Ethernet networks
• Aftermarket ADAS kit targets commercial vehicle retrofits
• BrainChip Announces Immediate Availability of Akida™ Pico for Remote Evaluation via FPGA Cloud
• RISC-V Pivots from Academia to Industrial Heavyweight
• SmartDV and Mirabilis Design Announce Strategic Collaboration for System-Level Modeling of SmartDV IP
• RISC-V IP Core Portfolio at Embedded World 2026, Powering Next-Gen Embedded Systems for Automotive, IoT & Industrial Systems…

Friday, February 13, 2026

• CEA and Soitec launch their collaborative area
• Synopsys to showcase AI-driven engineering innovation at India AI Impact Summit 2026
• Arteris Network-on-Chip Technology Achieves Deployment Milestone of 4 Billion Chips and Chiplets

Thursday, February 12, 2026

• Compartmentalisation by Microservices
• We CAN! Now in XL
• Rambus Announces Departure of Chief Financial Officer
• EnSilica to Highlight Complete Ku- and Ka-band User Terminal Chipset at MWC Barcelona 2026
• STMicroelectronics introduces the first automotive microcontroller with AI acceleration for edge intelligence
• Physical AI: Fueling the Next Wave of Semiconductor Growth
• Arteris Technology Deployed More Broadly by NXP to Accelerate Edge AI Leadership
• Keysight Enables Enterprise-Scale AI Adoption in Semiconductor Design with SOS Enterprise
• The Data Dilemma: Cracking the Code of Data Movement for the Next Wave of Semiconductor Innovation
• QuickLogic Corporation to Exhibit and Present at Chiplet Summit 2026
• EU launches NanoIC pilot line to oversee development of sub-2nm chips on the continent
• SkyeChip’s UCIe 3.0 Advanced Package PHY IP for SF4X Listed on Samsung Foundry CONNECT

Wednesday, February 11, 2026

• EU approves €3B German State aid for cleantech manufacturing
• Will the Global Foundry Landscape Be Shifted with Japan’s Revival?
• GlobalFoundries Reports Fourth Quarter 2025 and Fiscal Year 2025 Financial Results
• Ceva Wi-Fi 6 and Bluetooth IPs Power Renesas’ First Combo MCUs for IoT and Connected Home
• Cadence Unleashes ChipStack AI Super Agent, Pioneering a New Frontier in Chip Design and Verification

Monday, February 9, 2026

• RISC-V IP Core: T2M to Present Production-Proven RISC-V IP Core at Mobile World Congress, 2026
• Record quarter for Arm
• European firms eye investments in finance, semiconductors, AI in Vietnam
• STMicroelectronics expands strategic engagement with Amazon Web Services to enable new high performance compute infrastructure for cloud and AI data centers
• Inside FAMES: How Europe Depends on RTO Collaboration
• 2026 Outlook with Coby Hanoch of Weebit Nano
• Dnotitia Readies IPO After Turning AI Memory Bottlenecks into a New Semiconductor Category
• Biodegradable PCB targets short-lifetime electronics
• Tower Semiconductor & Nvidia team up on 1.6T silicon photonics for AI data centers
• Siemens unveils virtualised substation protection platform
• EnSilica joins CHERI Alliance to boost chip security
• Fabless Startup Aheesa Tapes Out First Indian RISC-V Network SoC
• FAMES pilot line inaugurated after delivering first validated semiconductor results
• Synopsys Lightmatter Alliance Highlights Bet On AI Chip Connectivity IP
• Chiplets Get Physical: The Days of Mix-and-Match Silicon Draw Nigh
• GF partners with Telsys to expand Israel presence
• TSMC to make advanced 3nm chips in Japan
• Phison Selects Andes RISC-V Cores for its First aiDAPTIV+ AI Solution, Marking a Major Milestone in AI Architecture
• VeriSilicon Enhanced ISP8200-FS Series IP Achieves ASIL B Functional Safety Certification
• Omni Design Technologies Advances 200G-Class Co-Packaged Optics IP Portfolio for Next-Generation AI Infrastructure
• Exclusive Interview: Mika Jäsberg Discusses CoreHW’s RTLS Offering