Search News

Sunday, December 19, 2021

• SiPearl awarded a €17.5M funding from the EIC Accelerator program
• Intel CEO Says Chip Shortage To Last Until 2023
• UK doubles venture capital investment in tech
• Taiwan approves TSMC fab investment plan in Japan
• Teledatics Introduces World's First Open Wi-Fi "HaLow" Development Platform
• Imagination's Series3NX neural network accelerator helps UNISOC to create 5G smartphone platform
• Teledatics Introduces World's First Open Wi-Fi
• Creonic GmbH is Heavily Invested in the Expansion and Research of 6G Technologies
• SiPearl awarded a ?17.5M funding from the EIC Accelerator program
• Imagination appoints Carol Chesney to board as non-executive director
• Hardent VESA DSC IP Cores Licensed by Teledyne LeCroy for DisplayPort Test Solution
• PCIe 5.0 & PCIe 4.0 PHYs and Controller IP Cores are available for immediate licensing to maximize your Interface speed for complex SoCs

Thursday, December 16, 2021

• Kandou Closes $75 Million in Series D Funding
• Gowin Automotive-grade FPGAs Pass SAIC's 2500h Heat Resistance Tests
• TSMC Introduces N4X Process

Wednesday, December 15, 2021

• Samsung and IBM reveal plans to make next-generation CPU with 5 nm process
• StarFive Released Open-Sourced Dubhe Linux SDK in RVspace Community
• Kandou Delivers USB-C Multiprotocol Retimer Product Family for USB4 Support
• TSMC Presents 2021 Excellent Performance Award to Outstanding Suppliers
• Synopsys Initiates $200 Million Accelerated Share Repurchase Agreement
• Synopsys SiliconSmart Library Characterization Solution Achieves Certification for TSMC N5, N4 and N3 Advanced Processes
• 3Q21 Revenue of Global Top 10 IC Design (Fabless) Companies Reach US$33.7 billion, Four Taiwanese Companies Make List, Says TrendForce
• Lattice Expands Automate Solution Stack and Propel Design Tool Capabilities to Accelerate Industrial Application Development
• Atomic Rules introduces the world's highest performance PCIe host interface for Intel Agilex F-Series FPGAs
• Cliosoft Selected for Rapid Assured Microelectronics Prototypes (RAMP) Program
• Secure Thingz and Intrinsic ID Partner to Ensure Supply Chains of Trust for the Embedded Industry
• MediaTek Dimensity 9000 uses Armv9 technology for unparalleled performance
• Industry's fastest TLS accelerator ready to boost Xilinx Versal platform
• TSMC Newest N4X Process Targets HPC Products

Tuesday, December 14, 2021

• Intel CEO trip to Taiwan seeks to secure TSMC 3nm supply: analyst
• Benchmarking Neuromorphic Computing: Devil Is in the Details
• Phase-change memory comes to 18nm FDSOI
• Maven Silicon - ARM Approved Training Partner
• IBM, Samsung Unveil VTFET to Extend Moore's Law
• FPGA Development Opens Up
• Ultra-Low power GNSS Multi-Constellation Digital IP core available for Battery powered IoT devices and Smart Wearables SoC application

Monday, December 13, 2021

• Security Standards Are a Must for Consumer IoT
• The Status of AI at the Edge? It's Complicated
• New RISC-V verification product changes the fabric of processor DV
• MIPI M-PHY Update Doubles Peak Data Rate for Next-Generation Flash Memory Storage Applications
• SEMIFIVE Acquires Hanatec
• Semi Capex on Pace for 34% Growth in 2021 to Record $152.0 Billion
• IC Manage Launches Holodeck on AWS Marketplace for Instant Cloud Bursting

Sunday, December 12, 2021

• Imec demonstrates successful monolithic integration of Schottky diodes and depletion-mode HEMTs with 200 V GaN-IC
• Silex Insight to divest their video business to Audinate
• Hisense Enters Into MPEG LA's AVC Patent Portfolio License
• Siemens' new mPower solution gains certification for TSMC's N7 and N5 technologies
• CXL Put Through Its Paces
• CEVA and Mimi Hearing Technologies Partner to Democratize Assistive Hearing for the True Wireless Earbuds Market
• 10/100/1000M Ethernet PHY IP Core in ST 28FDSOI technology licensed to a leading Chinese Semiconductor company for Broadband Access Networks Application
• MoSys Partners with Silicom to Provide Stellar Packet Classification IP Optimized for Intel FPGA-Based SmartNICs and Infrastructure Processing Units
• Arasan announces the immediate availability of its ultra-low power MIPI D-PHY IP for the GlobalFoundries 12nm FinFET process node

Thursday, December 9, 2021

• Synopsys Approves Stock Repurchase Program with Authorization Up to $1 Billion
• AST SpaceMobile Selects EnSilica to Support the Development of its Next Generation Advanced Cellular ASIC Chip
• Floadia Develops Memory Technology That Retains Ultra-high-precision Analog Data for Extended Periods
• TSMC November 2021 Revenue Report

Wednesday, December 8, 2021

• China's road to homegrown chip glory looks to be going for a RISC-V future
• With CHIPS Act, US Risks Building a White Elephant
• sureCore delivers ultra-low power register files with more than 50% less power than off-the-shelf versions
• IC Market Direction Indicator Points to 11% Growth in 2022
• Siemens collaborates with PDF Solutions to boost IC yield and speed time to market
• RISC-V Celebrates Incredible Year of Growth and Progress, Ratifying Multiple Technical Specifications, Launching New Education Programs, and Accelerating Broad Industry Adoption
• StarFive VisionFive Single Board Computer Officially for Sale, Accelerating RISC-V Ecosystem Development
• proteanTecs Expands into Mobile and Boosts Management to Accommodate Growth
• BMW Group Signs Agreement with Inova Semiconductor and GlobalFoundries to Secure Supply
• SEGGER adds 64-bit RISC-V support to Embedded Studio
• Intel Announces Intent to Take Mobileye Public
• Expedera Raises $18M Series A Funding to Advance Its Deep Learning Accelerator IP
• EU stops the clock on Nvidia-Arm investigation
• TSMC in spat with Intel

Tuesday, December 7, 2021

• BMW, GloFo sign chip supply agreement
• AMD may use Samsung's 4nm node for Chromebook processors
• StarFive Starts Delivery of High Performance RISC-V CPU Core IP "Dubhe"
• Webinar : USB 3.1 Gen2 Device Controller IP Core usage in Intel Quartus Prime Pro
• Avery Design Systems Offers Comprehensive Verification Support for the New HBM3 Interface Standard
• 5G New Radio Release-15 gNodeB reference design (includes L1-L2-L3) Stack for 5G Private Enterprise Networks, available for immediate licensing
• GUC Optimizes Quality of Results and Accelerates Time to Tapeout Using the Cadence Digital Full Flow
• NextChip Selects Rambus Security IP to Secure Apache6 Automotive Processor