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Sunday, December 5, 2021

• Mirabilis releases VisualSim AI Processor Designer
• Fraunhofer extends RISC-V embedded processor for edge AI
• What is Sensor Fusion?
• Imagination announces GPU licensing deal with YADRO
• Imagination launches RISC-V CPU family
• FortifyIQ Sets the Stage at the Design Automation Conference for Revolutionizing Chip Design with Pre-silicon Security Verification
• Breker Verification Systems Unveils System Coherency Synthesis TrekApp Building on Its Successful Cache Coherency Test Solution
• Imperas releases new RISC-V verification product that changes the fabric of processor DV
• Codeplay Software partners with Andes Technology to achieve Software First SoC Design for AI-based applications using RISC-V Vector Processors
• Ashling RiscFree now supports Andes Technology RISC-V CPUs
• GUC Monthly Sales Report - November 2021
• True Circuits Introduces New Synthesizable Precision PLL and Synthesizable Micro PLLs and DLLs and Demonstrates Silicon Proven DDR PHY
• Fraunhofer IPMS and CAST Announce a RISC-V Embedded Processor for Edge AI
• UMC Reports Sales for November 2021
• SDIO Host and Device Controller IP Cores with superfast I/O interlink and support for massive storage capacities is ready for immediate licencing
• Global Semiconductor Sales Increase 24% Year-to-Year in October
• True Circuits Attends Design Automation Conference

Thursday, December 2, 2021

• Ford, GlobalFoundries Aim to Boost Domestic IC Supplies
• Foundry Revenue Jumps 12% QoQ in 3Q2021
• Intel Looking to Deepen Ties with TSMC in Hopes of Securing 3nm Supply
• FTC Sues to Block $40 Billion Semiconductor Chip Merger
• CAST Introduces 8K Video Codecs and Advanced Image Signal Processing IP Cores
• Imagination B-Series GPU IP selected for Innosilicon graphics card

Wednesday, December 1, 2021

• Soitec acquires NovaSiC, strengthens SiC wafer technology
• HPMicro Semiconductor Announces the Release of the HPM6000 Series of Microcontrollers with AndesCore Dual D45 Cores
• SiFive Raises RISC-V performance bar with New Best-in-Class SiFive Performance P650 Processor
• Codasip appoints Ron Black as CEO
• RISC-V International Ratifies 15 New Specifications, Opening Up New Possibilities for RISC-V Designs
• Andes RISC-V Superscalar Multicore A(X)45MP and Vector Processor NX27V Upgrade Their Spec. and Performance
• Alphawave IP: Acquisition of Precise-ITC and completion of major milestones for China Product Partnership
• HPMicro Semiconductor Announces the Release of the HPM6000 series of Microcontrollers with AndesCore™ dual D45 cores
• Synopsys Extends Industry Leadership as Customers Surpass 500 Tapeouts Using Flagship Fusion Compiler Solution

Tuesday, November 30, 2021

• videantis achieves Automotive SPICE Level 2 certification
• Cadence Expands Collaboration with TSMC and Microsoft to Accelerate Timing Signoff for Giga-Scale Designs on the Cloud
• Arteris Announces Financial Results for the Third Quarter 2021 and Estimated Fourth Quarter and Full Year 2021 Guidance
• Agnisys Delivers Novel AI Technology and FPGA Support for IP and SoC Specification Automation
• First SoC ever to pass CC EAL5+ certification thanks to Tiempo Secure TESIC Secure Element IP
• Flex Logix Joins the Edge AI and Vision Alliance
• LeapMind Announces Efficiera v2 Ultra-Low Power AI Inference Accelerator IP
• Arasan Chip Systems announces Immediate availability of MIPI I3C PHY I/O IP

Monday, November 29, 2021

• Siemens Bags Three TSMC OIP Partner of the Year Awards for Next-gen Design Enablement
• Siemens Expands Collaboration with AWS to Facilitate Cloud-Based Digital Transformation for Industry
• Soitec and Mersen announce strategic partnership to develop new silicon carbide (SiC) substrates for the electric vehicle market
• Nvidia reportedly using TSMC N5 node for GeForce RTX 4000 Series
• IAR Systems and Codasip collaborate to enable low-power RISC-V based applications
• Key ASIC Signed LOI to Acquire Wafer FAB in The US
• Micron and UMC Announce Global Settlement
• CEO interview: Minima's Tuomas Hollman on why static timing sign-off is over
• USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP cores with Superfast speed and High-power efficiency for lag-less data processing is Silicon Proven and available in 8nm LPP for licensing
• MIPS selects Imperas Reference Models for RISC-V Processor Verification

Sunday, November 28, 2021

• Silicon Catalyst Partners with Sony Semiconductor Solutions to Accelerate Semiconductor Startups
• Synopsys Expands Use of AI to Optimize Samsung's Latest Mobile Designs
• intoPIX Unveils "TicoXS FIP" During its ProAV Virtual Event This Week
• Profile of a traceability tool promising automation in SoC designs

Thursday, November 25, 2021

• First RISC-V smartphones could launch in 2022

Wednesday, November 24, 2021

• WiLAN Subsidiary Acquires Wired Connectivity Patent Portfolio
• North American Semiconductor Equipment Industry Posts October 2021 Billings
• GPU shipments increase year-over-year in Q3
• SynSense and Prophesee partner to combine neuromorphic engineering expertise for developing one-chip event-based smart sensing solution for ultra-low power edge-AI
• Samsung Selects Texas as Site for $17 Billion Fab
• Siemens receives three 2021 TSMC OIP Partner of the Year awards for next-generation design enablement
• The Democratization of Chip Design
• AMIQ EDA Joins OpenHW Group and Contributes Linting Capabilities for CORE-V Open-Source RISC-V Cores and Testbenches

Tuesday, November 23, 2021

• SC21: Chinese Supercomputer Approaches Quantum Performance
• Samsung set to compete against TSMC with new foundry in US
• Do We Need 6G?
• Samsung choses Austin for $17bn 3nm fab
• VeriSilicon Image Signal Processor IP Achieved ISO 26262 Automotive Functional Safety Certification