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Sunday, June 7, 2020

• The aspects of 6G that will matter to wireless design engineers
• Configuring Processors In The Field
• GUC Monthly Sales Report - May 2020
• Sampling of 2Q Semiconductor Sales Guidance Now At -5%
• UMC Reports Sales for May 2020
• Andes Technology Steps Up to Premier Membership in RISC-V International; Greatly Expanding its U.S. R&D and Field Application Engineering Staffing
• Mentor joins the O-RAN ALLIANCE to help drive interoperability requirements for 5G network silicon

Friday, June 5, 2020

• Auto Sector Stuck in Neutral as a Few IC Makers Recover

Thursday, June 4, 2020

• Huawei's proposal to replace TCP/IP is going nowhere fast

Wednesday, June 3, 2020

• Nolam Embedded Systems discloses the MIL-STD1553 solution integrated on REFLEX CES Arria 10 SoC Module
• IAR Systems launches support for the RISC-V P extension for Packed-SIMD instructions
• SmartDV Delivers New Design IP for Video, Imaging, Entertainment System Protocols
• Synopsys Accelerates FIPS 140-3 Certification with NIST-Validated True Random Number Generator IP

Tuesday, June 2, 2020

• Former General Manager of GlobalFoundries China joins SMIC
• Lattice Accelerates FPGA-Based Processor Design With New IP Ecosystem and Design Environment
• The Increasingly Ordinary Task Of Verifying RISC-V
• GPU Market Provides a Ray (Tracing) of Hope
• Green Hills Software Adds Industry-Leading Advanced Software Development Tools Support for RISC-V
• Cadence Achieves Digital and Custom/Analog EDA Flow Certification for TSMC N6 and N5 Process Technologies
• Efinix Announces Availability of Three RISC-V SoCs
• Synopsys Introduces Industry's First Complete USB4 IP Solution
• MIPI Alliance Completes Development of A-PHY v1.0, an Industry-Standard Long-Reach SerDes Physical Layer Interface for Automotive Applications
• Enyx launches an ultra-low latency development framework for building standardized, FPGA-based trading systems
• Securing the Internet of Things in a Quantum World
• MediaTek Will Not Illegally Supply TSMC Chips To Huawei
• SMIC plans to raise $2.8 billion as the US tries to hamper China's Semiconductor growth

Monday, June 1, 2020

• Collaboration focuses on development tools for RISC-V-based MCUs
• PUFsecurity IP Open Source Program: Bridging the Gap in Chip Security
• NEUCHIPS Announces World's First Deep Learning Recommendation Model (DLRM) Accelerator: RecAccel
• First-Quarter 2020 Global Semiconductor Equipment Billings Up 13 Percent Year-Over-Year
• UltraSoC enables ultra-high-speed closed-chassis analytics and debug over Synopsys USB3
• Codasip Extends SweRV Support Package to Include Western Digital SweRV EH2 & EL2 RISC-V Cores
• GigaDevice GD32 MCU and Amazon AWS Launch New Embedded Cloud Platform
• Imagination announces next-generation IEEE 802.11ax/Wi-Fi 6 IP for low-power applications

Sunday, May 31, 2020

• Don't Let Baggage Hinder Innovation: RISC-V Lets Us Start with a Clean Slate
• DARPA Marries IC Security with System-Level Synthesis
• Dolphin Design unveils SPIDER, a turnkey platform to accelerate the design of energy efficient power management systems
• Global Semiconductor Sales Decrease 1.2 Percent Month-to-Month in April
• Synopsys Fusion Design Platform and DesignWare IP Selected by Baikal Electronics to Deliver Latest High-Performance Computing SoC
• Ambarella Adopts Cadence Clarity 3D Solver for AI Vision Processor Development
• Cloud Computing Is Changing Everything About Electronic Design
• Seamless Microsystems announces a major design-win
• Samsung Foundry Certifies Synopsys Design Compiler NXT for 5/4nm FinFET Process Technologies

Thursday, May 28, 2020

• eInfochips collaborates with EchoNous Inc. to develop the recently FDA-cleared KOSMOS platform
• Imagination's GPU selected by SemiDrive for automotive chip
• Texas Instruments Maintains Firm Grip As World's Top Analog IC Supplier

Wednesday, May 27, 2020

• What's So Important About Processor Extensibility?
• Domain-Specific Processors Enable More Than Moore
• How On-Premises Enhances your Chances of IoT Success
• DARPA Looks to Automate Security for IC Design
• Synopsys' Silicon-Proven DesignWare DDR IP for High-Performance Cloud Computing Networking Chips Selected by NVIDIA
• Khronos Group Releases OpenVG 1.1 Lite to Bring High-Quality Vector Graphics to OpenGL ES 2.0-Compatible GPUs
• Chip Equipment Becomes Trade War's Latest Battlefield
• TSMC Delivers World-first 7nm Automotive Design Enablement Platform
• TSMC to move 5nm Plus process to volume production in 4Q20

Tuesday, May 26, 2020

• SI semi forecast is -6% in 2020; +10-15% in 2021
• 5G? Wait 'Til Next Year
• Lattice and Etron Deliver Small, Low Power Reference Design for Edge AI and Video Processing Applications
• Domain Specific Accelerators Will Drive Vector Processing on RISC-V
• UltraSoC and Canis Labs partner to secure the CAN bus
• Menta joins PROMISE Consortium under the Horizon 2020 Initiative of the European Commission
• Synopsys Announces Support of TensorFlow Lite for Microcontrollers on Energy-Efficient ARC EM and ARC HS Processor IP
• GOWIN Semiconductor Integrates their latest HDMI/DVI RX and TX IP into GOWIN EDA IP Generator
• Cadence to Optimize Digital Full Flow and Verification Suite for Arm Cortex-A78 and Cortex-X1 CPU Mobile Device Development