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Wednesday, February 5, 2020

• Embedded controller Floating-Point Library supports RISC-V
• UMC Announces 14nm certification on Mentor's Calibre Eco Fill Flow
• Acquisition Rebound Lifts 2019 to Third-Largest M&A Year
• Presto Engineering Acquires DELTA Microelectronics Business from FORCE Technology

Tuesday, February 4, 2020

• When ADAS Goes People-Blind
• GreenWaves GAP9 AI/IoT ULP app processor on GF's 22FDX to sample H1 2020; mass production 2021
• GigaDevice Launches the New GD32E232 Series of MCU's Featuring the Arm Cortex-M23 core for Embedded Systems
• GUC Monthly Sales Report - Jan 2020
• Gartner Says Worldwide Semiconductor Spending Declined in 2019 Due to Slowing Macroeconomy and Falling Memory Prices
• 2019 Global Silicon Shipments Dip From 2018 Record High But Revenue Remained Stable Above $11 Billion, SEMI Reports

Monday, February 3, 2020

• Making Kynisys: how we're building the future of AI
• TI's First Automotive SoC with an AI Accelerator Launches
• The First RISC-V Hackathon in Israel
• Synapse Design's Continued Fast Growth Drives Opening of Two Offshore Semiconductor Design Centers
• Worldwide Semiconductor Sales Decrease 12 Percent to $412 Billion in 2019
• Arteris IP FlexNoC Interconnect and Resilience Package Licensed by SiEngine for ISO 26262-Compliant Automotive Systems
• China Maintains Chip Output in Wake of Virus Outbreak
• SmartDV Achieves Record Revenue in 2019

Sunday, February 2, 2020

• University of Pittsburgh researchers explore enabling lag-free connections in massive IoT devices
• UMC Announces 14nm certification on Mentor's Calibre Eco Fill Flow
• Supply Chain Poised for Coronavirus Disruption
• Qorvo Acquires UWB Chip Provider Decawave for $400m
• UltraSoC extends its commitment to Japanese market with appointment of Ryoden
• Semiconductor R&D To Nudge Higher Through 2024
• JEDEC Publishes Update to Universal Flash Storage (UFS) Standard
• Chips&Media Pioneering With The World's First Real-time Multi-Standard Decoder, including AV1, HW IP, WAVE517

Wednesday, January 29, 2020

• High-Bandwidth Accelerator Access to Memory: Enabling Optimized Data Transfers with RISC-V
• Creonic Joins German Center for Satellite Communications (DESK)
• Xilinx Reports Fiscal Third Quarter 2020 Results
• Digital Blocks AMBA Multi-Channel DMA Controller IP Core Family Extends Leadership with targeted applications in DMA Streaming of Video and Data over PCIe or UDP/IP Network Interface.

Tuesday, January 28, 2020

• EU announces strict 5G guidelines amid security risks
• UK Approves Huawei 5G Equipment with Restrictions
• Lattice Semiconductor Showcases Low Power FPGA-based AI/ML Solutions at tinyML Summit
• Thales unveils Cybels Analytics AI-based platform to detect complex cyberattacks
• SoM is built around multi-core RISC-V SoC FPGA

Monday, January 27, 2020

• Ethernet Enables Higher Data Rates for Space Applications
• Intel Moving Select CPU Manufacturing to GlobalFoundries
• QuickLogic Announces Restructuring Plan to Reduce Operating Expenses in Order to Achieve Profitability Goals for Fiscal Year 2020
• Arteris IP Adds 17 New Licensees, Revenue Exceeds $31M in 2019
• Rambus Reports Fourth Quarter and Fiscal Year 2019 Financial Results
• Cobham Gaisler successfully verifies its first RISC-V processor, NOEL-V, using Aldec's Riviera-PRO for HDL Simulation

Sunday, January 26, 2020

• Why Imagination Technologies has joined the FIDO Alliance
• Former Google and Tesla Engineer Chris Lattner to Lead SiFive Platform
• proteanTecs Announces Live Webinar on In-Field Failure Prediction Based on IC Deep Data Monitoring
• Flex Logix EFLX 1K eFPGA Core Design Kits Available Now For TSMC 40nm ULP And 40nm LP Process Technologies
• Kneron raises $40m for next-gen Edge AI chip
• WiLAN Awarded $85.23M in Apple Re-Trial

Saturday, January 25, 2020

• ESP Open Source Research Platform Enables the Design of RISC-V & Sparc SoC's with Accelerators