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Wednesday, October 30, 2019

• The Linley Group Microprocessor Report Highlights BrainChip's Akida™ Spiking-Neural-Network Processor
• China IC 'Big Fund' Phase II Aims Self-Sufficiency
• DMP adopted for NEDO project of "Survey of issues for finding ideas regarding Technology Development for AI Chip and Next-generation Computing for High-efficiency and High-speed Processing"
• China GDP and PMI Contraction A Risk Factor For Global Economy
• How to Choose Between AI Accelerators
• CEVA Appoints Bernadette Andrietti to its Board of Directors
• AI Takes Over Linley Fall Processor Conference
• Cadence Presented with Four 2019 TSMC Partner of the Year Awards
• Rambus Achieves Industry-Leading GDDR6 Performance at 18 Gbps

Tuesday, October 29, 2019

• Synopsys and AMD Execute Multi-Year ZeBu Emulation Agreement
• Silex Insight Fast-track FIPS 140-2 Certification with NIST-Validated Crypto Coprocessor
• GLOBALFOUNDRIES Appoints Amir Faintuch as SVP and General Manager Leading Computing and Wired Infrastructure Business

Monday, October 28, 2019

• David Zinsner Appointed to Credo Board of Directors
• Adesto Joins STMicroelectronics Partner Program to Accelerate Time-to-Market for Customers
• Pre-Silicon Security Assessment
• TSMC and GLOBALFOUNDRIES Announce Resolution of Global Disputes Through Broad Global Patent Cross-License
• Synopsys Ships More Than 3,000 HAPS-80 Prototyping Systems
• Achronix and BittWare Launch VectorPath Accelerator Card with Speedster7t FPGAs
• 'The AI Inference Processor is Dead'
• Hex Five Adds MultiZone Security Isolation with Micron's Authenta Flash
• AIC Semiconductor Licenses CEVA's 802.11ax Wi-Fi 6 IP for IoT Connectivity
• Optima Design Automation Launches with Focus on Next-Generation Semiconductor Functional Safety Tools
• Synopsys Accelerates Cloud Computing SoC Designs with New Die-to-Die PHY IP in Advanced 7nm FinFET Process
• Arm to Deliver CHERI-based Prototype to Tackle Security Threats

Sunday, October 27, 2019

• PathPartner Technology to Showcase Driver and Passenger Safety Solutions at TU-Automotive Europe
• Accellera Announces Standardization Initiative to Address Design Automation and Tool Interoperability for Functional Safety
• Sofics Analog I/O's and ESD clamps proven for TSMC 16nm, 12nm and 7nm FinFET processes
• Gidel Provides 3x Acceleration of FPGA and ASIC Development and Validation for Vision and Image Processing
• Micron Introduces Comprehensive AI Development Platform
• North American Semiconductor Equipment Industry Posts September 2019 Billings
• Micron Introduces Industry's First Silicon-Based Security-as-a-Service Platform for IoT Edge Devices
• SiFive Announces New U8-Series Core IP For High-Performance Compute
• Dr. Necip Sayiner Joins Rambus Board of Directors
• Xilinx Envisions its Future Without Huawei
• NSITEXE Achieves First-Pass Silicon Success for High-Performance Data Flow Processor-based SoC Test Chip Using DesignWare IP

Wednesday, October 23, 2019

• RISC-V Challenges And Opportunities
• Veriest experts presenting at DVCon Europe Conference
• SiFive Announces New SiFive Shield For Modern SoC Design
• TensorFlow gets native support for PowerVR GPUs via optimised open-source SYCL libraries
• VeriSilicon Releases Most Advanced FD-SOI Design IP Platform on GLOBALFOUNDRIES 22FDX for Edge AI and IoT Applications
• Innosilicon's Broad IP Portfolio Qualified on GLOBALFOUNDRIES 12LP FinFET Platform for High-Performance Applications
• Renesas Expands Access to Portfolio of Leading-Edge IP Licenses
• AES Encryption IP Cores from CAST Receive NIST Certification

Tuesday, October 22, 2019

• Attopsemi Published Two Papers About Innovative I-fuse™ 0.4V/1uA read and 250°C Bake Reliability Data on 22nm FD-SOI at IEEE S3S Conference, 2019.
• The Crucial Role of PUF in AIoT Security
• TSMC Outlines 5nm Plans, 7nm and EUV Progress
• Astera Labs Accelerates PCI Express 5.0 System Deployment in Collaboration with Intel and Synopsys
• New Arm IP brings intelligent, immersive experiences to mainstream markets

Monday, October 21, 2019

• GCC support for the draft Bit Manipulation Extension for RISC-V
• Dialog further extends IoT influence, acquires Creative Chips for $80m cash
• Cadence Announces First-to-Market NVMe 1.4 Verification IP for High-Performance Computing
• BrainChip Awarded New Patent for Artificial Intelligence Dynamic Neural Network
• Chips&Media Delivers The World's First Commercial AV1 Hardware Decoder IP, WAVE510A
• CEVA Celebrates Wireless IoT Milestone, Surpassing 100 Licensing Deals for its Bluetooth and Wi-Fi Technologies
• USC ISI The MOSIS Service and Samsung Foundry collaborate to spur microelectronics innovation in the US
• Cadence Reports Third Quarter 2019 Financial Results
• Synopsys Launches New ARC VPX DSP Processor IP for High-performance Signal Processing SoC Designs
• Microchip's Low-Power Radiation-Tolerant (RT) PolarFire FPGA Enables High-Bandwidth Space Systems with Lower Total System Cost
• PHY Wireless Launched to Address Today's Real World Cellular Location and Capacity Challenges
• Rambus Closes Sale of Payments and Ticketing Businesses to Visa
• OPENEDGES and INNOSILICON unveil advanced DDR Controller and DDR PHY integrated IP solutions

Sunday, October 20, 2019

• Shanghai FD-SOI Forum 2019 – the Full Recap
• TSMC Recognizes Synopsys with Four "Partner of the Year" Awards
• Samsung wants to rally more fabless customers