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Thursday, October 3, 2019

• CAN to TSN Gateway from CAST Bridges CAN 2.0/FD Buses with Time Sensitive Ethernet

Wednesday, October 2, 2019

• NXP Launches the GHz Microcontroller Era
• Los Alamos National Laboratory Teams with Arm to Develop Tailored, Efficient Processor Architectures
• Silicon Creations Named 2019 TSMC Partner of the Year for Analog / Mixed-Signal IP
• Synopsys Completes Acquisition of QTronic GmbH
• IP Controller Core CAN 2.0b and CAN FD of Fraunhofer IPMS certified according to ISO security standard

Tuesday, October 1, 2019

• Adesto and Cadence Collaborate to Expand xSPI Ecosystem for Emerging IoT Devices
• M31 Technology Won TSMC's 2019 Partner of the Year Award for Specialty Process IP
• Xilinx Announces Vitis - a Unified Software Platform Unlocking a New Design Experience for All Developers

Monday, September 30, 2019

• Announcing the Winners of the RISC-V Soft CPU Contest
• How big data and IoT initiatives render the 'garbage in, garbage out' theory invalid
• Andes Technology and Tiempo Secure Announce Strategic Partnership to Enhance RISC-V Platform Security up to CC EAL5+ Certification
• Global Semiconductor Sales Down 15.9 Percent Year-to-Year in August
• HDL Design House Appoints Frank Werner as Worldwide Sales Director
• TSMC Files Complaints Against GlobalFoundries in U.S., Germany and Singapore for Infringement of 25 Patents to Affirm its Technology Leadership and to Protect Its Customers and Consumers Worldwide
• SmartDV Adds Support for Verilator Open Source HDL Verilog Simulator

Sunday, September 29, 2019

• AI-Based Soft Switching Cuts Losses to Extend EV Range
• Accurate Current Detection for Motor Control, Battery Life
• Software infuses AI into high-performance computing
• Going All-in with Edge AI
• Globalfoundries to IPO
• Gen-Z Physical Layer Specification 1.1 now available for download
• UltraSoC selected by Japan's NSITEXE for automotive development
• Titan IC to Accelerate Pattern and String Matching on Mellanox's New BlueField-2 I/O Processing Unit (IPU) Device
• Synopsys Introduces PrimeECO Solution for Zero-Iteration Signoff-Driven Design Closure
• SiFive Enables Embedded Vision With New DesignShare Partners
• XMOS secures $19M funding to accelerate growth
• Live webinar from Dolphin Design: Pushing the limit of SoC energy efficiency with a NEW secret technique
• New Lattice CrossLinkPlus FPGAs Accelerate and Enhance Video Bridging for World-class MIPI-based Embedded Vision Systems
• Huawei & Arm Meet Behind Closed Doors
• Total Wafer Shipments to Drop 6 Percent in 2019, Resume Growth in 2020, Set New High in 2022, SEMI Reports

Thursday, September 26, 2019

• GLOBALFOUNDRIES Appoints Michael Hogan as SVP and General Manager to Support New Market Engagement Strategy
• Data Compression Accelerators from CAST Now Available on Xilinx Alveo Boards
• Sofics releases pre-silicon analog I/O's for high-speed SerDes for TSMC N5 process technology
• Multiple Mentor product lines now certified on TSMC's most advanced processes
• GLOBALFOUNDRIES Achieves More Than $1 Billion in Design Wins for 45RFSOI Solution for Mobile and Wireless Infrastructure Applications

Wednesday, September 25, 2019

• New Version of Most Widely Used Camera and Imaging Interface - MIPI CSI-2 - Designed to Build Capabilities for Greater Machine Awareness
• Synopsys and TSMC Collaborate to Develop Portfolio of DesignWare IP for TSMC 5nm FinFET Plus (N5P) Process
• Arm and TSMC Demonstrate Industry's First 7nm Arm-based CoWoS Chiplets for High-Performance Computing
• Moortec to Showcase its Advances in Embedded PVT Monitoring IP for 40nm-5nm at 2019 TSMC Open Innovation Platform Ecosystem Forum in Santa Clara
• SiFive Announces Key Enablement Of Trace And Debug
• Analog Bits Showcases Silicon of Analog and Mixed Signal IP Products on TSMC N7 Process Targeting Automotive Grade with Split Corner Lots and PVT Characterization Results Available
• Synopsys and TSMC Collaborate for Certification on 5nm Process Technologies to Address Next-generation HPC, Mobile Design Requirements
• Adesto Reaches Shipment Milestone of One Billion Non-Volatile Memory Devices
• Truechip Announces First Customer Shipment of CXL Verification IP
• Rambus Tapes Out 112G XSR SerDes PHY on Leading-edge 7nm Process
• TSMC's Leading-Edge Fab Investments Set Stage for Sale Surge in 2H19
• Lattice Semiconductor and Synopsys Renew Partnership on FPGA Synthesis Tools

Tuesday, September 24, 2019

• Alibaba unveils new AI chip aimed at speeding up e-commerce and cloud computing tasks
• No-Shows Blight AI Hardware Summit
• Moortec to Showcase its Advances in Embedded PVT Monitoring IP for 40nm-5nm at 2019 TSMC Open Innovation Platform® Ecosystem Forum in Santa Clara
• Cadence Digital and Signoff Full Flow and Custom/Analog Tools Certified for TSMC N6 and N5/N5P Process Technologies
• Andes and Dover Microsystems Partner to Deliver Professional Network Security Solution for RISC-V
• Evaluation Boards Now Available for Flex Logix EFLX4K eFPGA on GLOBALFOUNDRIES' Most Advanced FinFET Platform
• Breker Verification Systems Unveils Intelligent Regression Optimization Solution to Accelerate Simulation, Emulation Execution
• M31 Technology Develops Optimized IP Solutions on Multiple TSMC Specialty Processes
• Kandou Secures $56 Million in Series C Funding
• UMC Receives Final Approval for 100% Acquisition of Mie Fujitsu Semiconductor
• European Space Agency Selects AdaCore's Qualified Multitasking Solution for Spacecraft Software Development
• Achronix Joins TSMC IP Alliance Program
• Synopsys Extends Portfolio of Cloud Computing IP with 112G Ethernet PHY for Hyperscale Data Center SoCs
• CEO Leaves Wave, Putting MIPS' Future in Doubt
• Veriest announces opening of Budapest office

Monday, September 23, 2019

• Tessolve Proudly Announces The Launch Of 'Qubo' By It's Parent Company Hero Electronix
• Synergy between the Arm ecosystem and OCP communities to support the growth of compute infrastructure
• Analog Bits and Aragio Solutions Team Up with GLOBALFOUNDRIES to Deliver Automotive IP Solutions
• GLOBALFOUNDRIES Introduces 12LP+ FinFET Solution for Cloud and Edge AI Applications
• eMemory Wins 2019 TSMC IP Partner of the Year Award
• Andes Technology Features 32-bit A25MP and 64-bit AX25MP RISC-V Multicore Processors With Andes Custom Extension at TSMC 2019 Open Innovation Platform Ecosystem Forum
• CSEM joins GLOBALFOUNDRIES' FDXcelerator Program bringing ultra-lowPower IP to 22FDX process

Sunday, September 22, 2019

• North American Semiconductor Equipment Industry Posts August 2019 Billings
• Dolphin Integration becomes Dolphin Design
• Moortec Drives Optimised Performance & Increased Device Reliability on TSMC's N5 and N5P Process Technologies with its Complete In-Chip Monitoring Subsystem
• eSilicon Announces Availability of 7nm High-Bandwidth Interconnect (HBI+) PHY for Die-to-Die Interconnects
• Silicon Creations to Showcase PLL Developments on 22nm to 5nm Processes at TSMC 2019 Open Innovation Platform Ecosystem Forum
• Rambus Announces Portfolio of Advanced Memory and SerDes PHYs on TSMC N7 Process
• IAR Systems launches functional safety tools for STMicroelectronics' 8-bit MCUs
• Spectral Design and Test Inc., Announces a New Family of MemoryIP Targeted at the 5G Market
• Cambridge Consultants Becomes Arm Approved Design Partner
• Avery Design Partners with Marquee Semiconductor to Provide Sales, Support in India, and Deepens its Relationship to Prime Marquee's SoC Solution Platform
• Avery Design Introduces CXL VIP