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Thursday, March 26, 2020

• TSN Switch IP for GbE (10GbE)
• 100 IC Wafer Fabs Closed or Repurposed Since 2009
• Vervesemi Data converters for 5G applications Now Available on 8nm Process

Wednesday, March 25, 2020

• Vidatronic and Everest Sales and Solutions Join Forces to Expand Sales Coverage Through Mexico and Central America
• Software-Based Encryption at Hardware Level for IoT Security delivered by IKV, based on Intrinsic ID's BroadKey
• Achronix Selects Synopsys' Leading DesignWare IP Solutions to Accelerate Development of High-Performance Data Acceleration FPGA
• New Microchip MCU Enables Secure Boot Protection from SPI Flash
• Rambus Licenses DPA Countermeasures to Utimaco

Tuesday, March 24, 2020

• Efficient computing for AI and autonomous cars
• Apple reportedly accelerating production relocation
• How 5G+AI+AR Will Create Next-Gen Protection Against Pandemics
• Artificial Intelligence, 5G: How Beijing is preparing for its post-coronavirus economic recovery
• Next-Generation of AI Processors Featured at Linley Spring Processor Conference
• TSMC may revise 2020 outlook
• ESD Alliance Reports EDA Industry Revenue Increase for Q4 2019
• SiFive Selects Synopsys Fusion Design Platform and Verification Continuum Platform to Enable Rapid SoC Design
• Synopsys above ARM in IP licensing revenue in 2019
• Stop, Cut or Maintain European Chip Production Amid Covid-19

Monday, March 23, 2020

• Neural net accelerates IC design placement
• Enea and Ampere Partner on Arm-based uCPE Solution for Telco Edge
• CEVA Announces DSP and Voice Neural Networks Integration with TensorFlow Lite for Microcontrollers
• InterMotion Technology boosts IP verification productivity for Lattice Semiconductor's CrossLink FPGA family using Aldec's Active-HDL
• Arteris IP FlexNoC Interconnect Again Licensed by NETINT Technologies for Codensity Enterprise SSD Controllers

Sunday, March 22, 2020

• 'Electronic Nose' Inspired by Neuromorphic Technology
• Intel Scales Neuromorphic Computer to 100 Million Neurons
• Faraday's 28Gbps SerDes IP Now Available on UMC's 28HPC Process
• Foundry Revenue Estimated to Grow by 30% YoY in 1Q20, while COVID-19 Pandemic May Hinder Future Market Demand, Says TrendForce
• Global Top 10 IC Designers' 2019 Revenues Drop by 4.1% YoY, as Industry Growth to Face Challenges from COVID-19 Pandemic in 2020, Says TrendForce
• India Doesn't Need Its Own Fab
• BrainChip and Socionext Provide a New Low-Power Artificial Intelligence Platform for AI Edge Applications
• Synopsys Delivers Industry's First Ethernet 800G Verification IP for Next-Generation Networking and Communications Systems

Wednesday, March 18, 2020

• RISC-V is Here to Stay
• Data Demands Drive Co-Packaged Silicon and Optics for Switch Fabrics
• Inomize Selects Synopsys' Silicon-Proven 56G Ethernet PHY IP for High-Performance Computing and Communications SoC Design
• COVID-19 To Have Significant Effect on Worldwide Semiconductor Market in 2020, According to IDC

Tuesday, March 17, 2020

• Covid-19: The Power of Big Data and AI
• Intel Scales Neuromorphic Research System to 100 Million Neurons
• Open source of trouble: China's efforts to decouple from foreign IT technologies
• Trace and debug claim for RISC-V IP challenged by UltraSoC
• Blu Wireless announces the availability of its 60GHz mmWave evaluation kit
• New Highly Optimised LDPC Decoder in Software for Intel's FlexRAN Reference Software Will Increase Throughput by up to 3X
• TOSHIBA announced a Microcontroller employing Floadia's SONOS type Flash Memory IP "G1"
• Blu Wireless announces the availability of its 60GHz mmWave evaluation kit
• Codasip Awarded European Union Horizon 2020 Funding for Developing New RISC-V Processors

Monday, March 16, 2020

• Smart and Secure Embedded Solutions for IoT Design
• CEA-Leti Leading: Interview with CEO Emmanuel Sabonnadiere
• Chip making goes on at GlobalFoundries amid coronavirus
• Apple partner TSMC considers building powerful new chipsets in the U.S.
• Faraday Delivers System-Level ESD Protection Service to Reduce ASIC Time-to-Market
• Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput
• SiFive Launches Advanced Trace and Debug Portfolio, SiFive Insight
• Bragi and CEVA Collaborate to Redefine Hearable Devices
• SMIC Graduating from 14nm to Something Sort of Akin to 7nm
• Socionext Prototypes Low-Power AI Chip with Quantized Deep Neural Network Engine
• Cadence Elects Ita Brennan and Lewis Chew to Board of Directors

Sunday, March 15, 2020

• Covid-19 and The Success Story of Taiwan
• DAeRT: eInfochips' DFT Framework that Increases Productivity and Reduces Silicon Development Cycle
• Synopsys Unveils RTL Architect To Accelerate Design Closure
• eMemory Launches Reprogrammable NVM Solution on TSMC Platform