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Sunday, June 30, 2019

• Samsung Electronics and SK Telecom Advance in Bringing Korea Closer to 5G Standalone Commercialization
• Longtime X11/Linux Developer Joins SiFive To Work On RISC-V Processors
• Building an AI Platform for Medical Imaging System
• Inside Secure Announces Group Company Name, New Identity and New Trading Symbol
• Andes Technology and Silex Insight Announce Strategic Partnership for RISC-V Based Root-of-Trust IP Solutions
• Avery Design Systems Announces SimRegress and SimCompare
• SiFive Expands DesignShare IP Ecosystem to 20 Partner Companies
• Semiconductor Industry Capex Forecast to Slump in 2019 and 2020
• PLDA Reaches Key Milestone in Gen-Z IP Development
• GOWIN Semiconductor Introduces Their latest FPGA Product Line with Built-In Security
• AI Startup Preps Inference Chip

Wednesday, June 26, 2019

• Micron Cuts Capex, Wafer Starts
• Renesas Appoint New CEO
• Rambus Expands Family of CryptoManager Root of Trust Secure Silicon IP Cores
• BrainChip and Socionext Sign a Definitive Agreement to Develop the Akida Neuromorphic System-on-Chip

Tuesday, June 25, 2019

• Cadence Announces First-to-Market DisplayPort 2.0 Verification IP
• VESA Publishes DisplayPort 2.0 Video Standard Enabling Support for Beyond-8K Resolutions, Higher Refresh Rates for 4K/HDR and Virtual Reality Applications
• Mentor's Veloce Strato emulation platform selected by Iluvatar CoreX for verification of AI chips and software
• Aspinity Enables 10x Less Power for Always-on Sensing
• MorningCore Technology License CEVA DSP for High Performance Wireless and Automotive Communication Platforms
• NanoSemi Relies on OneSpin Automated Formal Verification Tools to Verify SystemC Designs for 5G ASICs
• Real Intent Announces 10X+ Speedup & 5X Capacity Improvement for Ascent AutoFormal Automatic RTL Verification
• InAccel release world's first FPGA orchestrator

Monday, June 24, 2019

• Qualcomm Snapdragon 855 Becomes First Mobile SoC to Receive Smart Card Equivalent Security Certification
• Is Your AV Safe? Prove It
• Aspinity Puts Neural Networks Back to Analog
• SmartDV Adds New Verification IP to Support OpenCAPI Standard
• CEVA Introduces Fully-Integrated Wi-Fi Solution to Connect IoT Devices to the Alibaba Cloud
• Synopsys Expands Center of Excellence with Infineon to Deliver Virtualizer Development Kit for AURIX TC4x Automotive Microcontroller
• Visa to Acquire Rambus Payments Portfolio
• eMemory's NeoFuse Qualified on Winbond 25nm DRAM Process
• Arteris IP FlexNoC Interconnect Implemented in Uhnder Digital Automotive Radar-on-Chip

Sunday, June 23, 2019

• UltraSoC secures £5m investment to target safety and security applications with its embedded analytics
• Vidatronic Licenses Power Management Unit and Analog IP to Leading Semiconductor IP Company, Arm

Friday, June 21, 2019

• North American Semiconductor Equipment Industry Posts May 2019 Billings

Wednesday, June 19, 2019

• Western Digital Extends Openness of PlatformIO and Enhances its RISC-V Portfolio to Accelerate Data-Centric Innovation
• ON Semiconductor Completes Acquisition of Quantenna Communications
• "Video For Machines" Using MPEG's New CDVA Standard, On Gyrfalcon's Industry Leading Chips
• Purdue & TSMC Partner to Enhance Chip Security
• Attopsemi Technology's Notification of Office Relocation
• eSilicon, Samtec and Wild River Technology Offer High-Performance Communications Webinar

Tuesday, June 18, 2019

• Arm joins Trusted Computing Group, driving towards secure devices everywhere
• China sees Taiwan supply chain as alternative to IDMs for power IC devices
• CSEM and MIFS demonstrate world-record lows in energy consumption for a microcontroller
• Acacia Communications Adopts Cadence Palladium Z1 Enterprise Emulation Platform to Accelerate Optical Networking Development
• Nurlink Completes First Call on Commercial NB-IoT Network with its CEVA-powered eNB-IoT SoC
• U.S. Companies Dominate Worldwide IC Marketshare
• PCI-SIG Announces Upcoming PCI Express 6.0 Specification to Reach 64 GT/s