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Saturday, December 21, 2019

• 5 Pivotal Events in AI Chips in 2019
• Why the Memory Subsystem is Critical in Inferencing Chips

Thursday, December 19, 2019

• How RISC-V is creating a globally neutral, open source processor architecture
• North American Semiconductor Equipment Industry Posts November 2019 Billings
• NEC Selects Synopsys ZeBu Server 4 Emulation Solution for Super Computer Verification

Wednesday, December 18, 2019

• What Worked, What Didn't In 2019
• Microchip unveils details and opens early access program for RISC-V enabled low-power PolarFire SoC family
• Synopsys and Porsche Consulting Introduce a Framework for Accelerating Automotive Development for the Digital Future
• AI processing architecture to be on display at CES 2020
• FPGA Platform from Lattice Semi Sets a New Standard for Efficiency
• Industry Awards for SOI Luminaries at UCLouvain, Lattice, NXP & Soitec
• Xilinx Powers Baidu's Production-Ready ACU-Advanced Platform for Automated Valet Parking
• GreenWaves Unveils Groundbreaking Ultra-Low Power GAP9 IoT Application Processor for the Next Wave of Intelligence at the Very Edge
• Atmosic Technologies Raises $28.5 Million in Latest Round of Funding
• CEVA Puts Intuitive Motion Control in the Palm of Your Hand with New Sensor Fusion Solution for Consumer Handheld Devices
• Vidatronic Appoints New Member to Its Board of Directors
• videantis AI processor platform adopted for KI-FLEX autonomous driving chip
• eMemory Joins Arm Ecosystem for Secure IoT Chips
• Faraday Unveils New IoT SoC Platform to Accelerate Early-Stage ASIC Development

Tuesday, December 17, 2019

• Trust and data privacy remain consumers' biggest fears about connected cars
• Microchip PolarFire Takes a RISC (-V)
• Japan Symposium '19 Summaries Part 1 – 5G/RF-SOI
• After the biggest fall for 18 years, it's all going to get better, says SI
• Latest AI Algorithms Presented at NeurIPS
• Samsung to make chips for China's Baidu in notable first partnership
• Tortuga Logic Awarded Multi-Million Dollar DoD Contracts to Increase The Security and Assurance of Microelectronics
• Aldec Enhances Riviera-PRO's VHDL and UVVM Support
• SLX FPGA v2019.4 Delivers an Average of 45x HLS Performance Improvement
• Wind River Announces RISC-V Support for VxWorks RTOS
• Veriest instrumental in verification of Innoviz automotive LIDAR device

Monday, December 16, 2019

• Gartner: Blockchain is the perfect match for the IoT
• Lattice Semiconductor launched new low-power FPGA based on FD-SOI
• Intel Acquires Artificial Intelligence Chipmaker Habana Labs
• A Renaissance in the Emulation Business Is Nigh
• Apple Buys Image Fusion Startup Spectral Edge
• Mobiveil's PCI Express 4.0 Endpoint Controller Passes PCI-SIG Gold and Interoperability Testing
• Renesas Electronics Collaborates with Xilinx on Versal ACAP Reference Designs
• Global Fab Equipment Spending Rebounds in Second Half of 2019 with Stronger 2020 Projected, SEMI Reports
• Intrinsic ID Raises 2.5 Million Euros for Internet of Things Security

Sunday, December 15, 2019

• The 8 AI trends we're watching in 2020
• Nokia signs contract with TIM Brazil to launch IoT offer
• An Introduction to Machine Learning on Mobile
• Codasip Studio and Codasip CodeSpace 8.2 available
• How to multiply by 18 battery autonomy of voice control devices?
• Alma Technologies Announces Availability of a New Ultra-High Throughput JPEG 2000 Encoder IP Core
• Enflame leverages Mentor's Tessent DFT solutions for innovative cloud AI chip targeting neural network training
• Mentor collaborates with Arm on unique eMRAM test solution using Samsung FDSOI technology

Thursday, December 12, 2019

• Functional Safety on Arm – Beyond Automotive
• Breker Verification Systems Launches Unique RISC-V TrekApp for Automated, High-Coverage System Integration Test Suite Synthesis
• Aldec's new FPGA-based NVMe Data Storage Solution Targets High Performance Computing Applications
• INSPECTOR diagnostic and debug platform passed the PCIe 4.0 compliance
• Revenue Ranking of Global Top 10 IC Design Companies Shows U.S. Companies Having Divergent Performances in 3Q19, Says TrendForce
• CEA-Leti Builds Fully Integrated Bio-Inspired Neural Network with RRAM-Based Synapses & Analogue Spiking Neurons

Wednesday, December 11, 2019

• Codasip Teams Up with Western Digital to Support Adoption of Open-Source Processors
• Enflame Technology Announces CloudBlazer with DTU Chip on GLOBALFOUNDRIES 12LP FinFET Platform for Data Center Training
• Global Semiconductor Equipment Sales Forecast - 2020 Rebound, 2021 Record High
• All M31 Automotive IP Products Received ISO 26262 Certifications
• Lattice and SiFive Announce Collaboration to Allow Lattice FPGA Developers Easy Access to RISC-V Processors
• Enflame Technology Selects Rambus HBM2 Memory Subsystem Solution For Next-Generation AI Training Chip
• Calterah Semiconductor's Automotive Radar SoC Enters Mass Production Using Synopsys DesignWare ARC Processor IP
• MediaTek selects Nucleus RTOS for next-generation modem technology

Tuesday, December 10, 2019

• RISC-V grows globally as an alternative to Arm and its license fees
• Arm's 2020 predictions
• Lattice Unveils First FPGAs on FD-SOI
• Cobham Releases LEON5 Processor IP Core
• New Lattice CrossLink-NX FPGAs Bring Power and Performance Leadership to Embedded Vision and Edge AI Applications
• Industry Veteran Randy Allen Joins SiFive as Vice President of RISC-V Software
• AccelerComm Reduces 5G Latency by up to 16x with NR LDPC Channel Coding
• Lattice Announces New Low Power FPGA Platform
• Dialog Semiconductor and Flex Logix Establish Strategic Partnership for Mixed Signal Embedded Field-Programmable Gate Arrays (eFPGA)
• Cobham Releases RISC-V Processor IP Core
• SiFive Announces New Technologies for Mission-Critical and AI Markets

Monday, December 9, 2019

• RISC-V Xmas gifts: SiFive emits vector-enabled cores, Western Digital teases new SweRVs, VxWorks hugs ISA, Samsung rolls it into 5G...
• Microchip Unveils Family Details and Opens Early Access Program for RISC-V Enabled Low-Power PolarFire SoC FPGA Family
• INSPECTOR™ diagnostic and debug platform passed the PCIe 4.0 compliance
• NSITEXE Selects SmartDV TileLink Verification IP for RISC-V Based Applications
• PLDA Announces Augmented Presence in Asia with Increased R&D, Support and Sales, and a New Chinese Language Website
• Codasip Teams Up with Western Digital to Support Adoption of Open?Source Processors
• Attopsemi's I-fuse OTP IP Embedded into Melexis' Sensor ICs In Mass Production
• Creonic Continues to Extend its Leading SATCOM IP Core Portfolio
• Hex Five Announces General Availability of MultiZone Security for Linux - The First Commercial Enclave for RISC-V processors
• Global Unichip Corporation Uses Cadence Digital Implementation and Signoff Flow to Deliver Advanced-Node Designs for AI and HPC Applications
• TSMC November 2019 Revenue Report
• Andes Technology and Deeplite, INC. Join Forces To Deploy Highly Compact Deep Learning Models Into Daily Life