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Thursday, June 6, 2019

• Silex Insight now supports 1GbE, 2.5GbE & 10GbE with their AV over IP OEM boards
• GLOBALFOUNDRIES and Soitec Announce Multiple Long-term SOI Wafer Supply Agreements to Meet Accelerating Demand in 5G, IoT and Data Center
• SiFive Celebrates Historic 100 Design Win Milestone
• SiFive Secures $65.4 Million In Series D Funding
• Imperas delivers first RISC-V Simulator for new Vector and Bit Manipulation specifications to Lead Customers

Wednesday, June 5, 2019

• ARM gets a rival as AMD licenses graphics IP to Samsung
• Achronix Chooses Rambus GDDR6 PHY IP for Next-Generation FPGA
• Side-Channel Attacks on Embedded Processors
• OpenHW Group created and announces CORE-V family of open-source cores for use in high volume production SoCs
• Lattice Diamond 3.11 Software Adds Support for New MachXO3D FPGA
• GUC Monthly Sales Report - May 2019
• Communications IC Market to Again Surpass Computer IC Market

Tuesday, June 4, 2019

• Marvell Extends Strategic Partnership with Arm
• HBM2e Top Contender for AI Applications
• First steps towards a made-in-Europe high-performance microprocessor
• Faraday Adopts Synopsys SpyGlass Design Handoff Kit to Ensure High Design Quality
• Avery Design Systems Announces SimCluster GLS to Accelerate Gate-Level Sign-Off Simulations
• Inside Secure Releases Industry's First Tool to Quickly, Graphically Create Secure Crypto Architectures
• Global Semiconductor Sales Decrease 14.6 Percent Year-to-Year in April; 12 Percent Decrease in Annual Sales Projected for 2019

Monday, June 3, 2019

• NI, Tessolve, and Johnstech Collaborated To Develop A Quad-site mmWave 5G Packaged Test Solution
• Efabless Collaborates with GLOBALFOUNDRIES to Enable New IP Development Models for Emerging Applications
• Synopsys and GLOBALFOUNDRIES Collaborate to Develop Broad Portfolio of DesignWare IP for 12LP FinFET Process
• Avery Design Systems Announces SymXprop for X Accurate RTL Simulation
• Thalia DA attracts $2m investment to grow analog IP re-use platforms
• Synopsys Fusion Design Platform First to be Certified by Samsung Foundry for 5LPE Process with EUV Technology
• Cadence Expands Customer-Managed Cloud Options with New Cloud Passport Partner Program
• Cadence Introduces the Spectre X Simulator, a Massively Parallel Circuit Simulator Delivering Up to 10X Faster Simulation with the Same Golden Accuracy
• Socionext Adopts the Cadence Full-Flow Digital and Signoff Tools for 7nm Designs
• True Circuits Demonstrates Silicon Proven DDR 4/3 PHY at the Design Automation Conference
• Wave Computing and Imperas Introduce New MIPS Open Simulator - MIPSOpenOVPsim
• Analog Bits and GLOBALFOUNDRIES Deliver Differentiated Analog and Mixed Signal IP for High-Performance Mobile and Compute Applications
• First Quarter 2019 Worldwide Semiconductor Equipment Billings Drop 19 Percent Year-Over-Year
• Truechip Offering complimentary licenses of PCIe Gen 3 Verification IP
• ASPEED Technology adopts M31 Technology MIPI D-PHY IP to provide global 360-degree imaging SoC solution
• Omni Design Demos Hyperon 14-bit 1.2Gsps ADC at the 2019 Design Automation Conference in Las Vegas

Sunday, June 2, 2019

• SolidRun and Gyrfalcon Team Up to Accelerate On-Device AI Performance with Powerful New i.MX 8M Mini SOM
• AMD and Samsung Announce Strategic Partnership in Ultra Low Power, High Performance Graphics Technologies
• Fab Joint Venture Seen for 200 mm
• Mentor sets new software scaling benchmark for Semiconductor Design Workload on Microsoft Azure
• UltraSoC embedded analytics selected to support Wave Computing's TritonAI 64 IP platform
• Intel Says EUV Ready, Challenging
• Avatar Integrated Systems Physical Implementation Tool Certified on TSMC 7nm FinFET Process
• NXP to acquire Marvell's WiFi and Bluetooth Connectivity Assets
• Gyrfalcon offers Automotive AI Chip Technology
• Silvaco and Si2 Release Unique, Free 15nm Open-Source Digital Cell Library
• Infineon to acquire Cypress, strengthening and accelerating its path of profitable growth

Wednesday, May 29, 2019

• Synopsys Design and Verification Solutions Enable Astera Labs to Develop Industry's First PCIe 5.0 Retimer SoC
• Synopsys Extends Leadership with Enhanced Verification Continuum Platform
• Global top-3 memory vendors to see sales hit bottom in 2Q19, says Digitimes Research
• SMIC Delisting Raises Question Mark Over China Tech
• Moortec to Showcase its High Accuracy Embedded Sensing Fabric at DAC 2019 in Las Vegas
• Efinix and M31 Technology Corporation Partner to Address Demand for Emerging AI Edge Computing Requirements
• Pixilica Licenses SiFive's RISC-V Embedded Processor IP
• PCI-SIG Achieves 32GT/s with New PCI Express 5.0 Specification

Tuesday, May 28, 2019

• Q'comm Cites U.S. Security in Appeal
• Functional Safety for Automotive HMI Systems
• Renesas Electronics Offers Complete Automotive Integrated Cockpit Reference Solution Based on R-Car System on Chip
• Arm portrays its strategy for machine learning at the edge
• Edge AI Going Beyond Voice and Vision
• Mentor's new Calibre Recon functionality methodically analyzes "early draft" IC designs for faster verification
• Globalfoundries use AR Glasses in Fab
• Mixel MIPI D-PHY IP Integrated into Teledyne e2v Snappy CMOS Image Sensors
• Silvaco Announces Viola I0-X - 10X Faster I/O Pad Characterization for Nanometer Silicon
• BrainChip Announces the Availability of Advanced AI Intellectual Property
• MediaTek Unveils Groundbreaking New 5G SoC for First Wave of 5G Flagship Devices
• Google and eSilicon at DAC 2019: Doing EDA in the Cloud? Yes, It's Possible!

Monday, May 27, 2019

• Companies Pushing Open Source RISC-V Silicon Out to the Edge
• Arm unveils new solutions for premium smartphones in 2020
• Synopsys Introduces PrimeYield for 100X Faster SoC Yield Analysis and Optimization
• IC Compiler II with Advanced Fusion Technologies Delivers Optimal QoR and Reduces ECO Turnaround Time More Than 40% at Juniper Networks
• Cadence Launches Protium X1, the First Scalable, Data Center-Optimized Enterprise Prototyping System for Early Software Development
• NVIDIA Deploys the New Cadence Protium X1 Platform to Accelerate Software Development of Large-Capacity GPUs
• Sofics' clipping/scaling circuit enhances reliability of Near Field Communication (NFC) and other wireless interfaces
• Hex Five Adds MultiZone Security to the AdaCore Software Ecosystem

Monday, May 27, 2019

• Sankalp Semiconductor Expands International Operations in Japan

Sunday, May 26, 2019

• Faraday Showcases FinFET ASIC Solutions and SoCreative!V SoC Platform at DAC 2019
• Thinci Deploys Full Cadence Verification Suite for AI Designs, Accelerating Project Schedule by Months
• Credo First to Demonstrate 7nm, 112G XSR SerDes
• Synopsys and Arm Collaborate to Enable Tapeouts by Early Adopters of Arm's Latest Premium Mobile Processors
• eSilicon Technical Advisory Board Members Win Facebook Research Award
• Delivering next-generation AI experiences for the 5G world
• Cadence Full-Flow Digital and Signoff Tools Optimized for New 7nm Arm Cortex-A77 CPU
• TSMC to Keep Supplying Chips to Huawei
• OneSpin's Newest App Assures Quality of RISC-V Processor Cores for Safety-, Security-Critical Applications