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Thursday, May 23, 2019

• Intrinsic ID Secures EUR 11 Million Loan from European Investment Bank

Wednesday, May 22, 2019

• SmartDV Speeds Delivery of its New CXL Verification IP
• Synopsys Announces Software-driven SoC Power Analysis Solution, Enabling 1000X Faster Time-to-Results
• TSMC-Certified OIP Virtual Design Environment with Synopsys Tools Now Available on Google Cloud
• Synopsys Delivers 100X Faster Formal Verification Closure for AI, Graphics, and Processor Designs
• China vs. US: Tech Warfare Hurts All
• Taiwan's TSMC says chip shipments to Huawei not affected by U.S. ban
• Cut Off From ARM, x86, What CPU Architectures Can Huawei Use?
• AGIC Technology to Achieve In-Memory Computing for AI Edge Computation
• AnalogX Launches Ultra Low Power Interconnect SerDes IP Portfolio to Fuel Next-Generation I/O Connectivity
• Synopsys Posts Financial Results for Second Quarter Fiscal Year 2019
• IAR Systems takes RISC-V to the next level with launch of professional development tools with leading performance and ensured code quality
• CAST Expands Popular UDP/IP Networking Cores Line
• SmartDV Unveils First Verification IP to Support Ethernet TSN

Tuesday, May 21, 2019

• Arasan announces the immediate availability of its MIPI CSI-2 v2.1 IP supporting C-PHY v1.2 and D-PHY v2.1
• Sankalp Semiconductor to Exhibit at Design Automation Conference - 2019
• Arm Deals Massive Blow to Huawei
• After 2Q19 Bottom, Expectations Increase for a 3Q19 IC Market Rebound
• US Grants 90-Day Reprieve for Huawei Suppliers
• Fraunhofer IIS Licenses MPEG-H Audio Patents to LG Electronics
• North American Semiconductor Equipment Industry Posts April 2019 Billings
• MVSILICON License and Deploy CEVA Bluetooth IP in its latest Wireless Audio Platform

Monday, May 20, 2019

• Trump's Huawei ban raises hopes for Chinese chip suppliers
• PathPartner to Demonstrate its Advanced Automotive and Driver Monitoring Solution at Embedded Vision Summit 2019
• Autotalks Accelerates C-V2X Readiness Following Interoperability Testing and Successful Bench Tests
• Imagination GPU Joins SiFive RISC-V Design Ecosystem
• Synopsys ARC EV6x Vision Processor IP Named Best Processor of the Year by the Embedded Vision Alliance
• sureCore Appoints Cedric Plomion Global Sales Director
• Achronix Introduces Ground-Breaking FPGA Family, Delivering New Levels of Performance with Adaptability for High-Bandwidth Data Acceleration Applications
• Arteris IP and Wave Computing Collaborate on Reference Architecture for Enterprise Dataflow Platform
• Minima Processor names Semiconductor Veteran Tuomas Hollman as CEO
• Marvell to Acquire Avera Semi, Creating an Infrastructure ASIC Powerhouse
• Faraday Geared Up for Data Communication Applications in ASIC Development
• Innovative Logic USB IP Portfolio Strengthens RISC-V Ecosystem
• ClioSoft and Silvaco Collaborate to Integrate ClioSoft's SOS Design Data Management Platform with Silvaco's Analog Custom Design Tools

Sunday, May 19, 2019

• Cadence Palladium and Protium Platforms Enable Innovium to Accelerate First-Pass Silicon Success for the Data Center Market
• Lattice's New MachX03D FPGA Enhances Security with Hardware Root-of-Trust Capabilities
• INGChips selects Dolphin Integration's Power Management IP Platform for its ultra Low Power Bluetooth Low-Energy SoC in 40 nm eFlash
• CEVA Announces Availability of SLAM Software Development Kit for CEVA-XM Intelligent vision DSPs and NeuPro AI Processors
• Synopsys and Kudan Collaborate to Accelerate Development of Intelligent Computer Vision Processing SoCs

Thursday, May 16, 2019

• lowRISC Expands and Appoints New Members to the Board of Directors from Google and ETH Zurich
• Intel Recaptures Number One Quarterly Semi Supplier Ranking from Samsung

Thursday, May 16, 2019

• Synopsys and Compaq Announce First Simulation Model for New PCI-X Standard

Wednesday, May 15, 2019

• SmartDV Reduces Protocol Debug Time with Smart ViPDebug

Tuesday, May 14, 2019

• An Introduction to the RISC-V-Based SweRV Core
• Samsung Electronics' Leadership in Advanced Foundry Technology Showcased with Latest Silicon Innovations and Ecosystem Platform
• AI Chipmaker Hailo Releases Industry-Leading Deep Learning Processor
• Cadence Tapes Out 112G Long-Reach SerDes IP on Samsung Foundry's 7LPP Process Technology
• Making virtual more of a reality with the new Arm Mali-D77 display processor
• Cadence Announces Broad Next-Generation Memory Standard Support in Samsung Foundry's Advanced Process Technologies
• New Cadence Tensilica Vision Q7 DSP IP Doubles Vision and AI Performance for Automotive, AR/VR, Mobile and Surveillance Markets
• Silicon Labs Partners with Pulsic, Selecting Animate as Its Automated Layout Solution for Analog IC Designs
• eSilicon Announces Production Qualification of 5G Infrastructure ASIC
• TSMC board approves nearly US$4 billion for advanced-node manufacturing

Tuesday, May 14, 2019

• Synopsys and Arm Extend Collaboration to Fusion Compiler to Accelerate Implementation of Arm's Next-Generation Client and Infrastructure Cores

Monday, May 13, 2019

• When AI Goes Wrong
• Arm demonstrates new IoT test chip and board for highly efficient, secure IoT designs
• Tiempo Secure Joins Deutsche Telekom's nuSIM Partnering Network
• Eta Compute Awarded Additional Patent For Asynchronous Microprocessor Technology
• Cadence Custom/AMS Flow Certified for Samsung 28nm FD-SOI Process Technology
• EDA Vendors Spread Wings as Market Softens
• Wave Computing Adds MIPS32 microAptiv Cores to MIPS Open Program
• Arteris IP FlexNoC Interconnect and Resilience Package Licensed by Black Sesame for ISO 26262-Compliant AI Chips for ADAS
• Synopsys and Arm Extend Collaboration to Fusion Compiler to Accelerate Implementation of Arm's Next-Generation Client and Infrastructure Cores