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Friday, November 22, 2019

• SparkFun Picks SiFive's FE310 to Power RISC-V-Based RED-V Thing Plus, RED-V RedBoard Dev Boards

Wednesday, November 20, 2019

• SiFive Welcomes Stuart Ching As Chief Revenue Officer
• UltraSoC joins the OpenHW Group and extends its commitment to an open-source future for technology development
• SmartDV's Platform-Independent VIP Portfolio Ensures Seamless Coverage-Driven Verification Flow
• Renesas' R-IN32M4-CL3 IC Boosts Next-Generation Ethernet TSN, Linking IT and OT Seamlessly With CC-Link IE TSN

Tuesday, November 19, 2019

• Cadence Named the #1 Technology Company on Investor's Business Daily List of the Top 50 ESG Companies
• Attopsemi Technology Attended 4th Japan SOI Symposium and Presented a Talk "I-fuse: A Disruptive OTP Technology"
• Credo Joins Open Compute Project (OCP) to Accelerate 400G and Beyond Connectivity Solutions for Hyperscale Datacenters and Telecom
• Alereon Adopts Omni Design's Low Power Analog-to-Digital and Digital-to-Analog Converters for Ultra-Wideband Applications
• North American Semiconductor Equipment Industry Posts October 2019 Billings

Monday, November 18, 2019

• SMIC Proposed Issue of US$200 Million Zero Coupon Convertible Bonds
• ST signs up for more Cree silicon carbide wafers
• RISC-V Myths and More
• RISC-V Not So Risky
• UVM-AMS Working Group Formed to Standardize UVM Analog/Mixed-Signal Extensions
• EasyIC Design joins Arm Approved Design Partner Program
• Expanding Universe for HPC, NVIDIA CEO Brings GPU Acceleration to Arm
• IntelliProp to Demo World's First UPI to Gen-Z Load/Store Host Adapter at SC19
• Graphcore leveraged Mentor's Questa technologies to verify massive Colossus GC2 AI processor
• High-speed comms options enable in-life debug and optimization for datacenter, HPC and storage customers

Sunday, November 17, 2019

• RISC-V Markets, Security And Growth Prospects
• Jim Cable (pSemi) & Herb Huang (Ningbo Semi) Honored for Pioneering RF-SOI Work
• Intel announces open oneAPI initiative and development beta release with Data Parallel C++ language for programming CPUs, GPUs, FPGAs, and other accelerators
• ArchiTek Select SiFive and DTS-Insight To Enable Next-Generation AI Solution Development
• Moortec To Showcase Its Latest Embedded PVT Monitoring IP For 40nm-5nm At The 2019 ICCAD in Nanjing
• Synopsys Custom Compiler Adopted by Samsung Foundry to Accelerate IP Design for 5LPE Process Technology with EUV Technology
• NUVIA Raises $53 Million to Reimagine Silicon Design for the Data Center
• Faraday and UMC Collaborate to Launch a Complete Set of 22nm Fundamental IP
• Intel to Reclaim Number One Semiconductor Supplier Ranking in 2019

Thursday, November 14, 2019

• Gyrfalcon Unveils Fourth AI Accelerator Chip
• Diamond Design Software from Lattice Semiconductor Enables Enhanced Security Features for MachXO3D FPGAs
• Synopsys Completes Acquisition of DINI Group
• Gyrfalcon's New Chip Raises Bar (12.6 TOPS/W) on High Performance Edge AI with Lower Power Use

Wednesday, November 13, 2019

• Reduce TCO with Arm Based SmartNICs
• FlexIC Foundry enables custom flexible integrated circuit design
• Nordic Semiconductor unveils world's first dual Arm Cortex-M33 processor wireless SoC for the most demanding low power IoT applications
• Gyrfalcon Technology and Sensory Deliver Enhanced AI Biometric Access on Edge Devices

Tuesday, November 12, 2019

• Mirabilis Design unveils the first rapid prototyping platform for Artificial Intelligence Processors and Applications
• Secure-IC and Andes Technology jointly provide cybersecurity enhanced RISC-V cores
• Efinix Rolls Out Trion T120 FPGAs
• New Cadence UltraLink D2D PHY IP for Die-to-Die Connectivity Enables High-Performance Applications with Cost-Effective Packaging
• Rambus Announces Comprehensive PCI Express 5.0 Interface Solution

Monday, November 11, 2019

• Avnet Releases MaaXBoard for Embedded Computing, Edge AI Development
• TSMC Board of Directors Meeting Resolutions
• Silicon Wafer Area Shipments Fall for Fourth Consecutive Quarter
• Xilinx Vitis Unified Software Platform Now Available for Download
• SMIC Reports 2019 Third Quarter Result
• Mentor introduces Tessent Safety ecosystem to meet IC test requirements of the autonomous vehicles era
• Rianta Releases Ethernet MAC/PCS/FEC IP Suite for ASICs targeting Datacenter, Networking and 5G Mobile Infrastructure
• New Smart Meter using Adesto's Memory and Communications Technologies Begins Pilot Program in Africa and Middle East
• Aerendir Mobile Inc. and SiFive Inc. Collaborate to Accelerate the Adoption of AI-Enabled Processors
• Blaize Emerges from Stealth to Transform AI Computing
• Xilinx Announces the World's Highest Performance Adaptive Devices for Advanced ADAS and AD Applications
• Achronix to Showcase 7nm FPGA Solutions at SC19
• Synopsys DesignWare ARC Data Fusion IP Subsystem Incorporated by Himax in Their Artificial Intelligence WiseEye ASIC
• GOWIN Semiconductor Releases the First FPGA with Integrated Bluetooth Radio