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Thursday, September 26, 2019

• GLOBALFOUNDRIES Appoints Michael Hogan as SVP and General Manager to Support New Market Engagement Strategy
• Data Compression Accelerators from CAST Now Available on Xilinx Alveo Boards
• Sofics releases pre-silicon analog I/O's for high-speed SerDes for TSMC N5 process technology
• Multiple Mentor product lines now certified on TSMC's most advanced processes
• GLOBALFOUNDRIES Achieves More Than $1 Billion in Design Wins for 45RFSOI Solution for Mobile and Wireless Infrastructure Applications

Wednesday, September 25, 2019

• New Version of Most Widely Used Camera and Imaging Interface - MIPI CSI-2 - Designed to Build Capabilities for Greater Machine Awareness
• Synopsys and TSMC Collaborate to Develop Portfolio of DesignWare IP for TSMC 5nm FinFET Plus (N5P) Process
• Arm and TSMC Demonstrate Industry's First 7nm Arm-based CoWoS Chiplets for High-Performance Computing
• Moortec to Showcase its Advances in Embedded PVT Monitoring IP for 40nm-5nm at 2019 TSMC Open Innovation Platform Ecosystem Forum in Santa Clara
• SiFive Announces Key Enablement Of Trace And Debug
• Analog Bits Showcases Silicon of Analog and Mixed Signal IP Products on TSMC N7 Process Targeting Automotive Grade with Split Corner Lots and PVT Characterization Results Available
• Synopsys and TSMC Collaborate for Certification on 5nm Process Technologies to Address Next-generation HPC, Mobile Design Requirements
• Adesto Reaches Shipment Milestone of One Billion Non-Volatile Memory Devices
• Truechip Announces First Customer Shipment of CXL Verification IP
• Rambus Tapes Out 112G XSR SerDes PHY on Leading-edge 7nm Process
• TSMC's Leading-Edge Fab Investments Set Stage for Sale Surge in 2H19
• Lattice Semiconductor and Synopsys Renew Partnership on FPGA Synthesis Tools

Tuesday, September 24, 2019

• Alibaba unveils new AI chip aimed at speeding up e-commerce and cloud computing tasks
• No-Shows Blight AI Hardware Summit
• Moortec to Showcase its Advances in Embedded PVT Monitoring IP for 40nm-5nm at 2019 TSMC Open Innovation Platform® Ecosystem Forum in Santa Clara
• Cadence Digital and Signoff Full Flow and Custom/Analog Tools Certified for TSMC N6 and N5/N5P Process Technologies
• Andes and Dover Microsystems Partner to Deliver Professional Network Security Solution for RISC-V
• Evaluation Boards Now Available for Flex Logix EFLX4K eFPGA on GLOBALFOUNDRIES' Most Advanced FinFET Platform
• Breker Verification Systems Unveils Intelligent Regression Optimization Solution to Accelerate Simulation, Emulation Execution
• M31 Technology Develops Optimized IP Solutions on Multiple TSMC Specialty Processes
• Kandou Secures $56 Million in Series C Funding
• UMC Receives Final Approval for 100% Acquisition of Mie Fujitsu Semiconductor
• European Space Agency Selects AdaCore's Qualified Multitasking Solution for Spacecraft Software Development
• Achronix Joins TSMC IP Alliance Program
• Synopsys Extends Portfolio of Cloud Computing IP with 112G Ethernet PHY for Hyperscale Data Center SoCs
• CEO Leaves Wave, Putting MIPS' Future in Doubt
• Veriest announces opening of Budapest office

Monday, September 23, 2019

• Tessolve Proudly Announces The Launch Of 'Qubo' By It's Parent Company Hero Electronix
• Synergy between the Arm ecosystem and OCP communities to support the growth of compute infrastructure
• Analog Bits and Aragio Solutions Team Up with GLOBALFOUNDRIES to Deliver Automotive IP Solutions
• GLOBALFOUNDRIES Introduces 12LP+ FinFET Solution for Cloud and Edge AI Applications
• eMemory Wins 2019 TSMC IP Partner of the Year Award
• Andes Technology Features 32-bit A25MP and 64-bit AX25MP RISC-V Multicore Processors With Andes Custom Extension at TSMC 2019 Open Innovation Platform Ecosystem Forum
• CSEM joins GLOBALFOUNDRIES' FDXcelerator Program bringing ultra-lowPower IP to 22FDX process

Sunday, September 22, 2019

• North American Semiconductor Equipment Industry Posts August 2019 Billings
• Dolphin Integration becomes Dolphin Design
• Moortec Drives Optimised Performance & Increased Device Reliability on TSMC's N5 and N5P Process Technologies with its Complete In-Chip Monitoring Subsystem
• eSilicon Announces Availability of 7nm High-Bandwidth Interconnect (HBI+) PHY for Die-to-Die Interconnects
• Silicon Creations to Showcase PLL Developments on 22nm to 5nm Processes at TSMC 2019 Open Innovation Platform Ecosystem Forum
• Rambus Announces Portfolio of Advanced Memory and SerDes PHYs on TSMC N7 Process
• IAR Systems launches functional safety tools for STMicroelectronics' 8-bit MCUs
• Spectral Design and Test Inc., Announces a New Family of MemoryIP Targeted at the 5G Market
• Cambridge Consultants Becomes Arm Approved Design Partner
• Avery Design Partners with Marquee Semiconductor to Provide Sales, Support in India, and Deepens its Relationship to Prime Marquee's SoC Solution Platform
• Avery Design Introduces CXL VIP

Thursday, September 19, 2019

• CAST CAN 2.0/FD Bus IP is Safety-Ready with ISO 26262 Certification
• Attopsemi Technology Presented "I-fuse: Dream OTP Finally Comes True" and won the best Innovative IP award on IP SoC 2019 China
• Alphawave IP Announces Industry Veteran and Marvell Founder Dr. Sehat Sutardja Has Joined Its Board of Directors
• Intel Ships Stratix 10 DX FPGAs; VMware Among Early Partners
• Xilinx Announces Chief Financial Officer Transition

Wednesday, September 18, 2019

• Intensivate Engages SiFive's RISC-V Expertise to Develop Leading Accelerator
• 5G和电动汽车市场快速发展，SOI晶圆会缺货吗？
• Semiconductor Acquisitions Regain Momentum in 2019
• SEGGER Makes Its Entire Ecosystem of Tools Available for AndesCores
• ECOC 2019: eSilicon to Demonstrate 7nm 58G DSP-Based SerDes Over Seven-Meter and Three-Meter Samtec Cable Assemblies

Tuesday, September 17, 2019

• 5倍产能爬坡，FD-SOI的体量又庞大了一圈
• Compute Express Link Consortium (CXL) Officially Incorporates; Announces Expanded Board of Directors
• Faraday's SoC Projects Doubled for Three Consecutive Years
• Veriest kick-starts Formal Verification methodology at Valens

Monday, September 16, 2019

• Intrinsic ID Security Summit 2019
• LIWEST Becomes Latest Austrian Operator to Evolve IPTV Security with Verimatrix and Ocilion
• ESD Alliance Reports EDA Industry Revenue Increase for Q2 2019
• SmartDV Announces Availability of Ethernet TSN Design IP
• CEVA Introduces New AI Inference Processor Architecture for Edge Devices with Co-processing Support for Custom Neural Network Engines
• Alphawave IP Announces Industry Veteran and Marvell Founder Dr. Sehat Saturdja Has Joined Its Board of Directors
• Infineon and Synopsys Collaborate to Accelerate Artificial Intelligence in Automotive Applications
• Notes from 7th Shanghai FD-SOI Forum held on September 16, 2019
• Mixel's MIPI D-PHY IP Integrated into Microsoft's Azure Kinect DK Depth Camera