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Wednesday, September 25, 2024

• Alphawave Semi Wins Fifth Consecutive TSMC OIP Ecosystem Forum Partner of the Year Award
• Europe takes a quantum leap: LUMI-Q consortium signs contract to establish quantum computer in the Czech Republic
• Quside and PQShield Partner to Launch Integrated Quantum-Safe Cryptographic Solution for Enhanced Digital Security
• The paradox of semiconductors - EU governance between sovereignty and interdependence
• eMemory Won TSMC OIP Partner of the Year Award for the Outstanding Development of its NVM IP on Advanced Nodes
• EnSilica joins TSMC Design Center Alliance
• EXTOLL collaborates with BAE Systems as a Key Partner for High-Speed SerDes IP
• M31 Launches ONFi5.1 I/O IP on TSMC 5nm Process
• MIPI Alliance Releases A-PHY v2.0, Doubling Maximum Data Rate of Automotive SerDes Interface To Enable Emerging Vehicle Architectures
• SIAE Microelettronica Selects Ensilica as Key Partner to Design ASICs for Next-Generation Telecom Equipment
• Siemens extends collaboration with TSMC to advance integrated circuit and systems design
• Silicon Creations Awarded TSMC's 2024 Open Innovation Platform Partner of the Year for Mixed Signal IP
• Synopsys and TSMC Pave the Path for Trillion-Transistor AI and Multi-Die Chip Design
• TSMC and Cadence Collaborate to Deliver AI-Driven Advanced-Node Design Flows, Silicon-Proven IP and 3D-IC Solutions

Tuesday, September 24, 2024

• Boosting Efficiency and Reducing Costs: SilvacoÂ’s Approach to Semiconductor Fabrication
• CEA-Leti Announces Launch of FAMES Pilot Line As Part of EU Chips Act Initiative
• EU Launches €73M Quantum Chip Funding to Support Technological Sovereignty and Semiconductor Innovation
• Intel More Likely to Divest Units Than Seek Buyout
• Security Concerns Plague Emerging Chip Architecture
• Alphawave Semi and Arm to Present on Chiplets for Architecting Next-Generation Terabit AI Networks at the TSMC OIP Ecosystem Forum North America
• Certus Semiconductor releases I/O library in TowerJazz's 65nm process
• Introducing a Versatile 1G Ethernet PHY IP Core with BroadR-Reach™ Technology for Automotive and Industrial Applications
• Introducing a Versatile 1G Ethernet PHY IP Core with BroadR-Reachâ„¢ Technology for Automotive and Industrial Applications
• Preferred Networks Inc. adopts Siemens' PowerPro software for next-generation AI chip design
• Samsung develops automotive SSD based on 8th-generation V-NAND
• Silvaco Expands its Victory TCAD and Digital Twin Modeling Platform to Planar CMOS, FinFET and Advanced CMOS Technologies

Monday, September 23, 2024

• Intel's entire turnaround plan hinges on this one new chip family - Clearwater Forest pictured, Intel's first 18A chip slated for high-volume manufacturing
• Alphawave Semi and InnoLight Extend PCIe over Optics Collaboration with Demonstration of 128Gbps Gen 7.0 over Low Latency Linear Pluggable Optics at ECOC 2024
• Ceva and Edge Impulse Join Forces to Enable Faster, Easier Development of Edge AI Applications
• Dnotitia Announces Strategic MOU with VESSL AI to Pioneer Next-Generation AI Innovation
• GenAI v1-Q launched with 4 bits Quantization support to accelerate larger LLMs at the Edge
• GUC Announces Adoption of HBM3E IP by CSP Data Center
• Renesas Leads ADAS Innovation with Power-Efficient 4th-Generation R-Car Automotive SoCs
• SigmaSense Teams Up with Dolphin Design to Deliver Power Efficiency in their Advanced SDC300 Touch Controller

Sunday, September 22, 2024

• Codeplay Brings RISC-V Support to the oneAPI Construction Kit
• €10m for European IoT 5G satellites
• Alphawave Semi - Interim results for the six months ended 30 June 2024
• Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at TSMC 2024 North America Technology Symposium
• Analog Bits to Demonstrate Power Management and Embedded Clocking and High Accuracy Sensor IP at the TSMC 2024 Open Innovation Platform Ecosystem Forum
• Comcores and Extoll successfully completed the interoperability test of Comcores JESD204C IP core and Extoll SerDes PHY
• JEDEC® Adds to Suite of Standards Supporting Compute Express Link® (CXL®) Memory Technology with Publication of Two New Documents
• JEDEC® Adds to Suite of Standards Supporting Compute Express Link® (CXL®) Memory Technology with Publication of Two New Documents
• Omni Design Technologies extends partnership with EnSilica and expands Swift™ Data Converter IP portfolio
• Omni Design Technologies extends partnership with EnSilica and expands Swiftâ„¢ Data Converter IP portfolio
• RAAAM Memory Technologies and NXP Semiconductors Announce Collaboration to Implement High Density On-Chip Memory
• Synopsys Enters Definitive Agreement with Keysight Technologies For Sale of Optical Solutions Group
• TSMC and Samsung consider major chip manufacturing plants in UAE
• VyperCore plans 5nm RISC-V server chip and card
• XtremeSilica Successfully Ships First SDRAM Controller for Tapeout GF40nm

Thursday, September 19, 2024

• TSMC's Strategic Win: Full-Scale Semiconductor Production Starts Ahead of Schedule

Wednesday, September 18, 2024

• Advanced Packaging Drives New Memory Solutions for the AI Era
• Cryptomathic and PQShield form strategic alliance to offer PQC solutions for code signing and data protection in compliance with latest NIST and CNSA recommendations
• Synopsys Enters Definitive Agreement with Keysight Technologies For Sale of Optical Solutions Group

Tuesday, September 17, 2024

• Alphawave Semi to Showcase Latest Advances in AI Connectivity IP at ECOC 2024
• Cadence boss on what's wrong with India's semiconductor plan
• Cadence Tensilica HiFi 5 DSPs Used in NXP's Next-Gen Audio DSP Family
• Chiplet Summit 2024 Shows How Advanced Packaging Keeps Moore's Law Alive
• Cracks Emerge in U.S. CHIPS Act
• RaaS, a collaborative initiative, adopted Menta's eFPGA technology for RaaS Edge Computing platform
• SiFive Highlights Key Inflection Points Driving RISC-V Adoption for AI and Introduces Intelligence XM Series for AI Workload Acceleration

Monday, September 16, 2024

• Intel and AWS Expand Strategic Collaboration, Helping Advance U.S.-Based Chip Manufacturing
• Joachim Kunkel Joins Arteris Board of Directors
• Intel signs up AWS for AI chips, splits off foundry business
• More than 30 Projects, Overview of China's Semiconductor Industry Project Progress in 2024
• Ultralight Edge AI Platform Unveiled
• Andes core wins control slot in Rivos' RISC-V SoC
• Chinese researchers develop ultra-efficient AI processor
• How the FPGA Came To Be, Did General Electric invent the PLD and EPLD in 1971?

Monday, September 16, 2024

• Taking 5G into space

Sunday, September 15, 2024

• Arm Accelerates AI From Cloud to Edge With New PyTorch and ExecuTorch Integrations to Deliver Immediate Performance Improvements for Developers
• Expedera Appoints Siyad Ma as New CEO to Drive Expansion, Innovation
• intoPIX Pre-Releases New JPEG XS IP-Cores & SDK with Master and Proxy Encoding at IBC 2024
• Omni Design Technologies Partners with Aura Intelligent Systems on Next Generation Radar
• Thalia launches AI-powered Layout Automation software with AMALIA 24.3
• The CAN XL Controller IP Core with a complete safety package is now available for immediate licensing to high-end automotive and consumer applications
• A message from Intel CEO Pat Gelsinger to employees regarding the next phase of Intel's transformation

Saturday, September 14, 2024

• Samsung Secures US AI Chip Firm "Ambarella" Orders For Its 2nm Process, Signaling A Breakthrough