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Thursday, August 29, 2019

• Full support for first flash-based RISC-V microcontroller
• Intel Ships First 10nm Agilex FPGAs

Thursday, August 29, 2019

• Synopsys Initiates $100 Million Accelerated Share Repurchase Agreement

Wednesday, August 28, 2019

• Machine vision utilising artificial intelligence
• BFloat16 processing for Neural Networks on Armv8-A
• Researchers build RISC-V chip from carbon nanotubes
• Global Top Ten IC Design Companies for 2Q19 Ranked by Revenue Released, with Top Five Registering Revenue Fall, Says TrendForce
• Sean Fan Joins Rambus as Chief Operating Officer
• SMIC Announces Unaudited 2019 Interim Results

Tuesday, August 27, 2019

• Blockchain Bolstering the Internet of Things
• Homomorphic Encryption Finally Ready for Commercial Adoption
• AndesCore N22 RISC-V Core Supports RV32IMAC or RV32EMAC Instruction Sets
• Sofics releases pre-silicon analog I/O's for high-speed SerDes for 5nm FinFET technology
• Mellanox Technologies Selects Verimatrix Silicon IP to Secure Family of Chipsets
• Global Foundries/TSMC Wrangle Seen Dragging Industry Down

Monday, August 26, 2019

• Blog: AI's Memory Problem
• RISC-V Is Experiencing a Period of Optimism and Growth with Global Revenue Expected to Reach $1.1 Billion by 2025, According to Tractica
• RISC-V Bases and Extensions Explained
• Rambus Completes Acquisition of Northwest Logic, Extending Leadership in Interface IP
• Creonic Participates in National Research Project KI-Radar
• GigaDevice unveils the GD32V series with RISC-V core, in a brand new 32bit general purpose microcontroller
• sureCore Unveils Low Power Design Service
• TSMC Will Vigorously Defend its Proprietary Technology in Response to GlobalFoundries Complaints
• Arasan and Xilinx announce their design win in providing a Total UFS 3.0 Solution to Wuhan Jingce

Monday, August 26, 2019

• North American Semiconductor Equipment Industry Posts July 2019 Billings

Sunday, August 25, 2019

• GLOBALFOUNDRIES Files Patent Infringement Lawsuits Against TSMC In the U.S. and Germany
• Does Your AI Chip Have Its Own DNN?
• Sofics releases analog I/O's for high-speed SerDes in TSMC N5 FinFET technology

Friday, August 23, 2019

• Sankalp Semiconductor to present technical paper at CDNLive Bangalore

Thursday, August 22, 2019

• DARPA unveils first SSITH prototype to mitigate hardware flaws

Wednesday, August 21, 2019

• How to Design SmartNICs Using FPGAs to Increase Server Compute Capacity (WP017)
• Unlocking Cortex-A53's Safety Potential
• Creonic Demonstrates its Beyond 5G FEC IP at the EuCNC Conference
• Is It Time to Forget about Huawei?
• Meet EnSilica at TI Automotive, India 2019
• Porsche Invests in Israeli Startup TriEye to Increase Road Visibility and Safety
• HDL Design House Introduces Expandable SoC IoT Platform
• Qualcomm And LGE Enter Into a New Global Patent License Agreement
• Synopsys Posts Financial Results for Third Quarter Fiscal Year 2019
• Next Generation Video Codec Standard Proposed: MPEG Video Coding for Machines (VCM)

Tuesday, August 20, 2019

• Autonomous Robots Put to Work: The Top Five Robots in Common Use
• Intel unwraps its first chip for AI and calls it Spring Hill
• Xilinx Announces the World's Largest FPGA Featuring 9 Million System Logic Cells
• Western Digital's Long Trip from Open Standards to Open Source Chips
• Top-15 Semiconductor Suppliers' Sales Fall by 18% in 1H19

Monday, August 19, 2019

• MediaTek on track to unveil 5G SOCs
• Atmosic and QuickLogic Partner to Enable Always-On, Always-Listening Voice Interactivity in Audio and Sensor Processing Platform
• Arm TechCon 2019: Showcasing the New Era of Total Compute
• Codasip studio and Codasip Codespace 8.1 available
• Lauterbach to support JTAG debug for RISC-V Linux
• Will More-than-Moore Take Off in China?