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Tuesday, December 10, 2019

• RISC-V grows globally as an alternative to Arm and its license fees
• Arm's 2020 predictions
• Lattice Unveils First FPGAs on FD-SOI
• Cobham Releases LEON5 Processor IP Core
• New Lattice CrossLink-NX FPGAs Bring Power and Performance Leadership to Embedded Vision and Edge AI Applications
• Industry Veteran Randy Allen Joins SiFive as Vice President of RISC-V Software
• AccelerComm Reduces 5G Latency by up to 16x with NR LDPC Channel Coding
• Lattice Announces New Low Power FPGA Platform
• Dialog Semiconductor and Flex Logix Establish Strategic Partnership for Mixed Signal Embedded Field-Programmable Gate Arrays (eFPGA)
• Cobham Releases RISC-V Processor IP Core
• SiFive Announces New Technologies for Mission-Critical and AI Markets

Monday, December 9, 2019

• RISC-V Xmas gifts: SiFive emits vector-enabled cores, Western Digital teases new SweRVs, VxWorks hugs ISA, Samsung rolls it into 5G...
• Microchip Unveils Family Details and Opens Early Access Program for RISC-V Enabled Low-Power PolarFire SoC FPGA Family
• INSPECTOR™ diagnostic and debug platform passed the PCIe 4.0 compliance
• NSITEXE Selects SmartDV TileLink Verification IP for RISC-V Based Applications
• PLDA Announces Augmented Presence in Asia with Increased R&D, Support and Sales, and a New Chinese Language Website
• Codasip Teams Up with Western Digital to Support Adoption of Open?Source Processors
• Attopsemi's I-fuse OTP IP Embedded into Melexis' Sensor ICs In Mass Production
• Creonic Continues to Extend its Leading SATCOM IP Core Portfolio
• Hex Five Announces General Availability of MultiZone Security for Linux - The First Commercial Enclave for RISC-V processors
• Global Unichip Corporation Uses Cadence Digital Implementation and Signoff Flow to Deliver Advanced-Node Designs for AI and HPC Applications
• TSMC November 2019 Revenue Report
• Andes Technology and Deeplite, INC. Join Forces To Deploy Highly Compact Deep Learning Models Into Daily Life

Sunday, December 8, 2019

• Andes' Core has RISC-V Vector Instruction Extension
• WiLAN Subsidiary and CXMT Enter into License and Acquisition Agreements
• Rambus Completes Acquisition of the Verimatrix Silicon IP, Secure Protocols and Provisioning Business
• Verimatrix Completes Sale of its Silicon IP Business Unit to Rambus
• UMC Reports Sales for November 2019
• GUC Monthly Sales Report - Nov 2019
• Synopsys Posts Financial Results for Fourth Quarter and Fiscal Year 2019
• Xilinx Issues Statement in Response to Analog Devices Patent Infringement Lawsuit
• UltraSoC donates RISC-V trace implementation to enable true open-source development
• Andes Corvette-F1 N25 Platform Becomes one of the first RISC-V Platforms Qualified for Amazon FreeRTOS
• Tech Industry Heavyweight Joins SiFive - Manoj Gujral Tapped As SVP & GM of Silicon Business Unit

Thursday, December 5, 2019

• New Vidatronic CTO to Innovate and Scale Technology

Wednesday, December 4, 2019

• Taking Self-Driving Safety Standards Beyond ISO 26262
• Where Is The Edge AI Market And Ecosystem Headed?
• BrainChip and Tata Consultancy Services (TCS) jointly Present a Demonstration Featuring Its Akida Neuromorphic Technology Platform at NeurIPS 2019
• Andes 45-Series Expands RISC-V High-end Processors 8-Stage Superscalar Processor Balances High Performance, Power Efficiency, and Real-time Determinism with Rich RISC-V Ecosystem
• SiFive To Present New Technologies At RISC-V Summit 2019
• Andes certifies Imperas models and simulator as reference for new Andes RISC-V Vectors Core with lead customers and partners

Tuesday, December 3, 2019

• SOI Consortium 2019/20 New Members AMAT, Analog Bits, Antaios, Silicon Catalyst, SmarterMicro, Thalia
• Global Semiconductor Sales Increase 2.9 Percent Month-to-Month in October; Annual Sales Projected to Decrease 12.8 Percent in 2019
• Aldec's Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM
• Veriest marks 1st anniversary of meetup series with special event in Belgrade
• SmartDV's TileLink, Verilator VIP on Full Display at RISC-V Summit
• Andes Presents Ground-Breaking 27-Series Processor at RISC-V Summit 2019
• Third Quarter 2019 Worldwide Semiconductor Equipment Billings Jump 12 Percent, SEMI Reports
• Neoverse N1 makes debut in new AWS cloud instances

Monday, December 2, 2019

• D&R announces the opening of an IP Core Store to support Soft IP Cores sales to the Chinese market
• Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System Innovation
• Lift off: De-RISC to create first RISC-V, fully European platform for space
• RISC-V Foundation Founding Member Andes Technology Turns Platinum
• UNISOC and Imagination carry out strategic cooperation on AI based on IMG Series3NX neural network accelerator
• Imagination launches IMG A-Series: "The GPU of Everything"
• SiFive Learn Inventor Development System Now AWS Qualified
• Mixel Announces Immediate Availability of MIPI D-PHY v2.5 IP
• Think Silicon demonstrates early preview of Industry's first RISC-V ISA based 3D GPU at the RISC-V Summit
• Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications

Sunday, December 1, 2019

• Intel Completes Sale of Smartphone Modem Business to Apple
• EnSilica and Macnica Europe GmbH Sign Distribution Agreement for Custom ASIC Design and Supply Services
• UMC Announces 22nm Technology Readiness Following Silicon Validation on World's Smallest USB 2.0 Test Vehicle
• Dolphin Design is ISO 9001 and EN 9100 certified
• SiFive Announces SiFive Learn Initiative
• Moortec's In-Chip Monitoring Subsystem Supports Uhnder in Groundbreaking Digital Automotive Radar-on-Chip