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Wednesday, June 12, 2019

• Why do Enterprises favor private or hybrid IoT deployments over public clouds?
• Toshiba Selects Cadence Tensilica Vision P6 DSP as Image Recognition Processor for its Next-Generation ADAS Chip
• UltraSoC strengthens management team with appointment of CFO
• X-FAB and Efabless Announce Successful First Silicon of Raven, An Open-Source RISC-V Microcontroller
• Mythic Secures $30M in New Financing and Strengthens Leadership Team

Wednesday, June 12, 2019

• IC Compiler II with Advanced Fusion Technologies Delivers Optimal QoR and Reduces ECO Turnaround Time More Than 40% at Juniper Networks

Tuesday, June 11, 2019

• Media Alert: Cadence to Showcase Aerospace and Defense Solutions at the 2019 International Paris Air Show
• Gartner Identifies Five Challenges to Growth and Adoption for Virtual Customers
• Report: Apple Still Eyes Intel's Modem Business
• AI: Friend or Foe?
• Everspin Enters Pilot Production Phase for the World's First 28 nm 1 Gb STT-MRAM Component
• Synopsys Achieves ISO 9001 Certification for IP Quality Management System
• Global Fab Equipment Spending to Rebound in 2020 with 20 Percent Growth
• Magewell Selects Lattice Semiconductor ECP FPGA Family For Video Capture Devices

Monday, June 10, 2019

• India's IC Imports Grew Dramatically in 2018, and U.S.-China Trade Tensions Could be a Reason
• RISC-V Foundation Announces Call For Papers For The 2nd Annual RISC-V Summit
• The Point Where IoT, AI & Quantum Computing Intersect
• Cobham Releases New Instruction Simulator for Radiation Hardened Processors
• intoPIX Presents the Smart Path for AV Over IP at InfoComm 2019
• Intel to Acquire Barefoot Networks, Accelerating Delivery of Ethernet-Based Fabrics
• Dream Chip opened new ASIC Design Center in Eindhoven, Netherlands
• Silicon-Proven Arteris IP Ncore Cache Coherent Interconnect Implemented in Toshiba ISO 26262-Compliant ADAS Chip
• Logic Design Solutions Introduces the first NVMe Host IP on PolarFire FPGA
• HDL Design House Adds New Representative in Europe
• Gyrfalcon's 2803 Plai Plug Development Hardware Delivers 24 TOPS/W for AI From Edge to Cloud

Sunday, June 9, 2019

• Andes Technology Launches RISC-V FreeStart Program with its Commercial-Grade CPU N22
• UMC Reports Sales for May 2019
• Imperas and Metrics Collaborate to Jump Start RISC-V Core Design Verification Using Open Source Instruction Stream Generator
• TSMC May 2019 Revenue Report
• CEVA Collaborates with Ellisys to Achieve SIG Qualification for its Bluetooth 5.1 Low Energy IP
• Space Codesign Systems Announces Support of Zynq UltraScale+ MPSoC
• SingMai offer universal encoding and decoding of analogue video

Thursday, June 6, 2019

• Silex Insight now supports 1GbE, 2.5GbE & 10GbE with their AV over IP OEM boards
• GLOBALFOUNDRIES and Soitec Announce Multiple Long-term SOI Wafer Supply Agreements to Meet Accelerating Demand in 5G, IoT and Data Center
• SiFive Celebrates Historic 100 Design Win Milestone
• SiFive Secures $65.4 Million In Series D Funding
• Imperas delivers first RISC-V Simulator for new Vector and Bit Manipulation specifications to Lead Customers

Wednesday, June 5, 2019

• ARM gets a rival as AMD licenses graphics IP to Samsung
• Achronix Chooses Rambus GDDR6 PHY IP for Next-Generation FPGA
• Side-Channel Attacks on Embedded Processors
• OpenHW Group created and announces CORE-V family of open-source cores for use in high volume production SoCs
• Lattice Diamond 3.11 Software Adds Support for New MachXO3D FPGA
• GUC Monthly Sales Report - May 2019
• Communications IC Market to Again Surpass Computer IC Market

Tuesday, June 4, 2019

• Marvell Extends Strategic Partnership with Arm
• HBM2e Top Contender for AI Applications
• First steps towards a made-in-Europe high-performance microprocessor
• Faraday Adopts Synopsys SpyGlass Design Handoff Kit to Ensure High Design Quality
• Avery Design Systems Announces SimCluster GLS to Accelerate Gate-Level Sign-Off Simulations
• Inside Secure Releases Industry's First Tool to Quickly, Graphically Create Secure Crypto Architectures
• Global Semiconductor Sales Decrease 14.6 Percent Year-to-Year in April; 12 Percent Decrease in Annual Sales Projected for 2019

Monday, June 3, 2019

• NI, Tessolve, and Johnstech Collaborated To Develop A Quad-site mmWave 5G Packaged Test Solution
• Efabless Collaborates with GLOBALFOUNDRIES to Enable New IP Development Models for Emerging Applications
• Synopsys and GLOBALFOUNDRIES Collaborate to Develop Broad Portfolio of DesignWare IP for 12LP FinFET Process
• Avery Design Systems Announces SymXprop for X Accurate RTL Simulation
• Thalia DA attracts $2m investment to grow analog IP re-use platforms
• Synopsys Fusion Design Platform First to be Certified by Samsung Foundry for 5LPE Process with EUV Technology
• Cadence Expands Customer-Managed Cloud Options with New Cloud Passport Partner Program
• Cadence Introduces the Spectre X Simulator, a Massively Parallel Circuit Simulator Delivering Up to 10X Faster Simulation with the Same Golden Accuracy
• Socionext Adopts the Cadence Full-Flow Digital and Signoff Tools for 7nm Designs
• True Circuits Demonstrates Silicon Proven DDR 4/3 PHY at the Design Automation Conference
• Wave Computing and Imperas Introduce New MIPS Open Simulator - MIPSOpenOVPsim
• Analog Bits and GLOBALFOUNDRIES Deliver Differentiated Analog and Mixed Signal IP for High-Performance Mobile and Compute Applications
• First Quarter 2019 Worldwide Semiconductor Equipment Billings Drop 19 Percent Year-Over-Year
• Truechip Offering complimentary licenses of PCIe Gen 3 Verification IP
• ASPEED Technology adopts M31 Technology MIPI D-PHY IP to provide global 360-degree imaging SoC solution
• Omni Design Demos Hyperon 14-bit 1.2Gsps ADC at the 2019 Design Automation Conference in Las Vegas

Sunday, June 2, 2019

• SolidRun and Gyrfalcon Team Up to Accelerate On-Device AI Performance with Powerful New i.MX 8M Mini SOM
• AMD and Samsung Announce Strategic Partnership in Ultra Low Power, High Performance Graphics Technologies
• Fab Joint Venture Seen for 200 mm
• Mentor sets new software scaling benchmark for Semiconductor Design Workload on Microsoft Azure
• UltraSoC embedded analytics selected to support Wave Computing's TritonAI 64 IP platform
• Intel Says EUV Ready, Challenging
• Avatar Integrated Systems Physical Implementation Tool Certified on TSMC 7nm FinFET Process
• NXP to acquire Marvell's WiFi and Bluetooth Connectivity Assets
• Gyrfalcon offers Automotive AI Chip Technology
• Silvaco and Si2 Release Unique, Free 15nm Open-Source Digital Cell Library
• Infineon to acquire Cypress, strengthening and accelerating its path of profitable growth