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Wednesday, May 29, 2019

• Synopsys Design and Verification Solutions Enable Astera Labs to Develop Industry's First PCIe 5.0 Retimer SoC
• Synopsys Extends Leadership with Enhanced Verification Continuum Platform
• Global top-3 memory vendors to see sales hit bottom in 2Q19, says Digitimes Research
• SMIC Delisting Raises Question Mark Over China Tech
• Moortec to Showcase its High Accuracy Embedded Sensing Fabric at DAC 2019 in Las Vegas
• Efinix and M31 Technology Corporation Partner to Address Demand for Emerging AI Edge Computing Requirements
• Pixilica Licenses SiFive's RISC-V Embedded Processor IP
• PCI-SIG Achieves 32GT/s with New PCI Express 5.0 Specification

Tuesday, May 28, 2019

• Q'comm Cites U.S. Security in Appeal
• Functional Safety for Automotive HMI Systems
• Renesas Electronics Offers Complete Automotive Integrated Cockpit Reference Solution Based on R-Car System on Chip
• Arm portrays its strategy for machine learning at the edge
• Edge AI Going Beyond Voice and Vision
• Mentor's new Calibre Recon functionality methodically analyzes "early draft" IC designs for faster verification
• Globalfoundries use AR Glasses in Fab
• Mixel MIPI D-PHY IP Integrated into Teledyne e2v Snappy CMOS Image Sensors
• Silvaco Announces Viola I0-X - 10X Faster I/O Pad Characterization for Nanometer Silicon
• BrainChip Announces the Availability of Advanced AI Intellectual Property
• MediaTek Unveils Groundbreaking New 5G SoC for First Wave of 5G Flagship Devices
• Google and eSilicon at DAC 2019: Doing EDA in the Cloud? Yes, It's Possible!

Monday, May 27, 2019

• Companies Pushing Open Source RISC-V Silicon Out to the Edge
• Arm unveils new solutions for premium smartphones in 2020
• Synopsys Introduces PrimeYield for 100X Faster SoC Yield Analysis and Optimization
• IC Compiler II with Advanced Fusion Technologies Delivers Optimal QoR and Reduces ECO Turnaround Time More Than 40% at Juniper Networks
• Cadence Launches Protium X1, the First Scalable, Data Center-Optimized Enterprise Prototyping System for Early Software Development
• NVIDIA Deploys the New Cadence Protium X1 Platform to Accelerate Software Development of Large-Capacity GPUs
• Sofics' clipping/scaling circuit enhances reliability of Near Field Communication (NFC) and other wireless interfaces
• Hex Five Adds MultiZone Security to the AdaCore Software Ecosystem

Monday, May 27, 2019

• Sankalp Semiconductor Expands International Operations in Japan

Sunday, May 26, 2019

• Faraday Showcases FinFET ASIC Solutions and SoCreative!V SoC Platform at DAC 2019
• Thinci Deploys Full Cadence Verification Suite for AI Designs, Accelerating Project Schedule by Months
• Credo First to Demonstrate 7nm, 112G XSR SerDes
• Synopsys and Arm Collaborate to Enable Tapeouts by Early Adopters of Arm's Latest Premium Mobile Processors
• eSilicon Technical Advisory Board Members Win Facebook Research Award
• Delivering next-generation AI experiences for the 5G world
• Cadence Full-Flow Digital and Signoff Tools Optimized for New 7nm Arm Cortex-A77 CPU
• TSMC to Keep Supplying Chips to Huawei
• OneSpin's Newest App Assures Quality of RISC-V Processor Cores for Safety-, Security-Critical Applications

Thursday, May 23, 2019

• Intrinsic ID Secures EUR 11 Million Loan from European Investment Bank

Wednesday, May 22, 2019

• SmartDV Speeds Delivery of its New CXL Verification IP
• Synopsys Announces Software-driven SoC Power Analysis Solution, Enabling 1000X Faster Time-to-Results
• TSMC-Certified OIP Virtual Design Environment with Synopsys Tools Now Available on Google Cloud
• Synopsys Delivers 100X Faster Formal Verification Closure for AI, Graphics, and Processor Designs
• China vs. US: Tech Warfare Hurts All
• Taiwan's TSMC says chip shipments to Huawei not affected by U.S. ban
• Cut Off From ARM, x86, What CPU Architectures Can Huawei Use?
• AGIC Technology to Achieve In-Memory Computing for AI Edge Computation
• AnalogX Launches Ultra Low Power Interconnect SerDes IP Portfolio to Fuel Next-Generation I/O Connectivity
• Synopsys Posts Financial Results for Second Quarter Fiscal Year 2019
• IAR Systems takes RISC-V to the next level with launch of professional development tools with leading performance and ensured code quality
• CAST Expands Popular UDP/IP Networking Cores Line
• SmartDV Unveils First Verification IP to Support Ethernet TSN

Tuesday, May 21, 2019

• Arasan announces the immediate availability of its MIPI CSI-2 v2.1 IP supporting C-PHY v1.2 and D-PHY v2.1
• Sankalp Semiconductor to Exhibit at Design Automation Conference - 2019
• Arm Deals Massive Blow to Huawei
• After 2Q19 Bottom, Expectations Increase for a 3Q19 IC Market Rebound
• US Grants 90-Day Reprieve for Huawei Suppliers
• Fraunhofer IIS Licenses MPEG-H Audio Patents to LG Electronics
• North American Semiconductor Equipment Industry Posts April 2019 Billings
• MVSILICON License and Deploy CEVA Bluetooth IP in its latest Wireless Audio Platform

Monday, May 20, 2019

• Trump's Huawei ban raises hopes for Chinese chip suppliers
• PathPartner to Demonstrate its Advanced Automotive and Driver Monitoring Solution at Embedded Vision Summit 2019
• Autotalks Accelerates C-V2X Readiness Following Interoperability Testing and Successful Bench Tests
• Imagination GPU Joins SiFive RISC-V Design Ecosystem
• Synopsys ARC EV6x Vision Processor IP Named Best Processor of the Year by the Embedded Vision Alliance
• sureCore Appoints Cedric Plomion Global Sales Director
• Achronix Introduces Ground-Breaking FPGA Family, Delivering New Levels of Performance with Adaptability for High-Bandwidth Data Acceleration Applications
• Arteris IP and Wave Computing Collaborate on Reference Architecture for Enterprise Dataflow Platform
• Minima Processor names Semiconductor Veteran Tuomas Hollman as CEO
• Marvell to Acquire Avera Semi, Creating an Infrastructure ASIC Powerhouse
• Faraday Geared Up for Data Communication Applications in ASIC Development
• Innovative Logic USB IP Portfolio Strengthens RISC-V Ecosystem
• ClioSoft and Silvaco Collaborate to Integrate ClioSoft's SOS Design Data Management Platform with Silvaco's Analog Custom Design Tools

Sunday, May 19, 2019

• Cadence Palladium and Protium Platforms Enable Innovium to Accelerate First-Pass Silicon Success for the Data Center Market
• Lattice's New MachX03D FPGA Enhances Security with Hardware Root-of-Trust Capabilities
• INGChips selects Dolphin Integration's Power Management IP Platform for its ultra Low Power Bluetooth Low-Energy SoC in 40 nm eFlash
• CEVA Announces Availability of SLAM Software Development Kit for CEVA-XM Intelligent vision DSPs and NeuPro AI Processors
• Synopsys and Kudan Collaborate to Accelerate Development of Intelligent Computer Vision Processing SoCs