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Thursday, May 16, 2019

• lowRISC Expands and Appoints New Members to the Board of Directors from Google and ETH Zurich
• Intel Recaptures Number One Quarterly Semi Supplier Ranking from Samsung

Thursday, May 16, 2019

• Synopsys and Compaq Announce First Simulation Model for New PCI-X Standard

Wednesday, May 15, 2019

• SmartDV Reduces Protocol Debug Time with Smart ViPDebug

Tuesday, May 14, 2019

• An Introduction to the RISC-V-Based SweRV Core
• Samsung Electronics' Leadership in Advanced Foundry Technology Showcased with Latest Silicon Innovations and Ecosystem Platform
• AI Chipmaker Hailo Releases Industry-Leading Deep Learning Processor
• Cadence Tapes Out 112G Long-Reach SerDes IP on Samsung Foundry's 7LPP Process Technology
• Making virtual more of a reality with the new Arm Mali-D77 display processor
• Cadence Announces Broad Next-Generation Memory Standard Support in Samsung Foundry's Advanced Process Technologies
• New Cadence Tensilica Vision Q7 DSP IP Doubles Vision and AI Performance for Automotive, AR/VR, Mobile and Surveillance Markets
• Silicon Labs Partners with Pulsic, Selecting Animate as Its Automated Layout Solution for Analog IC Designs
• eSilicon Announces Production Qualification of 5G Infrastructure ASIC
• TSMC board approves nearly US$4 billion for advanced-node manufacturing

Tuesday, May 14, 2019

• Synopsys and Arm Extend Collaboration to Fusion Compiler to Accelerate Implementation of Arm's Next-Generation Client and Infrastructure Cores

Monday, May 13, 2019

• When AI Goes Wrong
• Arm demonstrates new IoT test chip and board for highly efficient, secure IoT designs
• Tiempo Secure Joins Deutsche Telekom's nuSIM Partnering Network
• Eta Compute Awarded Additional Patent For Asynchronous Microprocessor Technology
• Cadence Custom/AMS Flow Certified for Samsung 28nm FD-SOI Process Technology
• EDA Vendors Spread Wings as Market Softens
• Wave Computing Adds MIPS32 microAptiv Cores to MIPS Open Program
• Arteris IP FlexNoC Interconnect and Resilience Package Licensed by Black Sesame for ISO 26262-Compliant AI Chips for ADAS
• Synopsys and Arm Extend Collaboration to Fusion Compiler to Accelerate Implementation of Arm's Next-Generation Client and Infrastructure Cores

Sunday, May 12, 2019

• Case study: accelerated chip design for drones and cameras with Arm DesignStart
• Soitec expands its engineered substrate portfolio into GaN (Gallium Nitride) with the acquisition of EpiGaN nv
• Does a SCM Controller Need a Translation Table?
• PowerVR GPU and NNA available on SiFive platform
• Samsung Foundry Begins Partnership with Silvaco to Launch their Semiconductor IP Assets
• Moortec Support Canaan Creatives Mass Production ASIC on TSMC 7nm Process
• Amphion Semiconductor introduces 4K/UHD capable AV1 video decoder hardware IP extension to its Malone video decoder family
• Elektrobit and Synopsys Collaborate to Accelerate Automotive Electronic System Virtual Development
• Agile Analog secures $5M in funding to change the semiconductor industry
• Imagination Technologies joins SiFive's DesignShare Ecosystem, Enabling RISC-V users to access industry-leading IP

Thursday, May 9, 2019

• Intel Targets 2021 for 7 nm
• TSMC April 2019 Revenue Report
• Texas Instruments Widens Its Lead As World's Top Analog IC Supplier
• ON Semiconductor Executive Named to Alphacore Inc. Advisory Board
• ClioSoft Achieves TUV SUD Certification in Support of Automotive ISO 26262 Standard

Wednesday, May 8, 2019

• Imagination announces ray tracing technology for licensing
• CoreHW and RoodMicrotec to establish long-term supply chain partnership
• Imagination Tech to License Ray-Tracing IP as 5G Beckons
• Efinix Partners with Samsung to Develop Quantum eFPGAs on 10nm Silicon Process
• UMC Reports Sales for April 2019
• Algo-Logic Systems Delivers Ultra-Low-Latency Pre-Trade Risk Check (PTRC) Solution Powered by Xilinx
• SmartDV Appoints HyperSilicon Exclusive Sales Representative in China
• Wave Computing Appoints Industry Veteran Art Swift CEO
• SMIC Reports 2019 First Quarter Result
• eSilicon Tapes Out 7nm Combo PHY (HBM2/HBM2E/Low Latency) Test Chip

Tuesday, May 7, 2019

• At Dac 19 D&R demonstrates more Innovation and Intelligence in IPMS™
• Samsung Foundry Forum 2019: eSilicon to unveil 14nm switching and 5G infrastructure ASICs
• IC designers placing additional foundry orders in anticipation of 3Q19 boom
• GOWIN Semiconductor Joins Arm DesignStart Offering Free Arm Cortex-M Processors for its FPGA Product Families

Monday, May 6, 2019

• Toshiba adds Cortex-M4 core MCUs
• Marvell Doubles Down on Automotive Ethernet
• How connected technology can help solve the supply chain challenges
• OneSpin Joins The RISC-V Foundation
• SmartDV Heads to ChipEx2019 in Israel with Extensive Design and Verification IP Portfolio
• eSilicon Tapes Out 7nm neuASIC IP Platform Test Chip
• Cadence Delivers Smart JasperGold Formal Verification Platform
• Fudan Microelectronics Group Selects Synopsys' DesignWare Bluetooth IP for Smart IoT System-on-Chips
• Codasip Presence at upcoming events: China Roadshow, DAC 2019, and RISC-V Workshop Zurich
• Cycle-accurate trace boosts performance optimization capabilities of UltraSoC embedded analytics infrastructure
• Arteris IP FlexNoC & Resilience Package Licensed by Semidrive for ISO 26262-Compliant Autonomous Driving Chips

Sunday, May 5, 2019

• GUC Monthly Sales Report - Apr 2019
• Sankalp Semiconductor to Exhibit at ChipEx - 2019
• OPENEDGES NoC (Network on Chip) Interconnect IP & DDR Controller licensed by ASICLAND
• PRO DESIGN Launches Intel Arria 10-Based Product Family of FPGA-Based Prototyping Systems
• ON Semi Acquiring GF Fab Deemed a Win-Win
• CEVA, Inc. Announces First Quarter 2019 Financial Results
• Blu Wireless raises $16.6 million in growth funding round for 5G applications