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Wednesday, August 7, 2019

• Western Digital Announces Technology Leadership Transition
• SMIC Reports 2019 Second Quarter Results
• CEVA, Inc. Announces Second Quarter 2019 Financial Results
• UMC Reports Sales for July 2019
• Faraday Leads Industry with 28G Programmable SerDes at 28nm for Networking ASIC
• Forming a Benchmark for ML at the Edge
• 76% of IC Products Expected to See Flat/Negative Growth in 2019
• UltraSoC strengthens global team with appointments in Asia and USA
• Arm Revenues Up, Royalties Down

Tuesday, August 6, 2019

• RISC-V Roadshow in Europe, Sep 16-26, 2019
• GLOBALFOUNDRIES and Arm Demonstrate High-Density 3D Stack Test Chip for High Performance Compute Applications
• VeriSilicon Launches VIP9000, New Generation of Neural Processor Unit IP
• Synopsys to Acquire QTronic GmbH

Monday, August 5, 2019

• China Looks At RISC-V As A Viable Replacement For Proprietary CPU Architecture Amid Trade War Tensions
• Gartner: AI will drive business value by supporting human decisions
• Taking Constrained ML to the Next Level
• Enhancing System Architecture Implementation for AI Applications, Microchip Delivers its Analog Embedded SuperFlash Technology
• Xilinx Expands Alveo Portfolio with Industry's First Adaptable Compute, Network and Storage Accelerator Card Built for Any Server, Any Cloud
• Andes Records Rapid Growth of RISC-V Processors Licensing Agreements in the First Half of 2019
• Eta Compute Appoints Dr. Ted Tewksbury Chief Executive Officer
• Mid-Year Global Semiconductor Sales Down 14.5 Compared to 2018
• Cadence and UMC Collaborate on Certification of Analog/Mixed-Signal Flow for 28HPC+ Process
• CEVA and Immervision Enter into Strategic Partnership for Advanced Image Enhancement Technologies

Sunday, August 4, 2019

• Intel Expands Workload Acceleration with Hewlett Packard Enterprise in New Programmable Acceleration Card
• Everspin Expands Spin-transfer Torque MRAM Ecosystem Support for its 1 Gigabit STTMRAM with Cadence Design IP and Verification IP
• Intel 10nm Chip Gets Mixed Reviews
• InAccel's Accelerated ML suite boosts Spark ML as much as 7x using Intel's Arria FPGAs
• GUC Monthly Sales Report - July 2019
• Avery Design Systems Announces SimAccel FPGA Accelerator
• Arasan to demonstrate its SD Card UHS-II PHY IP and eMMC 5.1 PHY IP for 12nm SoC Designs at the 2019 Flash Memory Summit

Wednesday, July 31, 2019

• A Pillar Of Sparks: Interview With The RISC-V Foundation
• Silvaco Appoints Babak Taheri as new Chief Executive Office
• Startup Puts AI Core in SSDs
• Arm brings automation to IoT connectivity management
• Mobiveil to Demonstrate its Latest SSD IP Solutions at Flash Memory Summit 2019
• China, Huawei Hit Q'Comm Where it Hurts
• Silvaco, Inc. Appoints Babak Taheri as CEO Succeeding David Dutton who assumes Role of Board Vice-Chair
• Silvaco Appoints Babak Taheri as new Chief Executive Officer
• Agile Analog Awarded Innovate UK Grant to Accelerate Semiconductor IP Development
• PLDA Announces Major PCIe 5.0 Design Win on Cutting Edge 5nm Process Node
• Kalray announces the Tape-Out of Coolidge on TSMC 16NM process technology

Tuesday, July 30, 2019

• Apple's iPhone Sales Down Again
• Blocking 5G from mmWave Will Limit its Potential, GSMA Warns
• RISC-V EMEA Roadshow Spotlight: MINRES Technologies
• Tessolve Highlights Test Engineering Practices, Participating At The ITC India 2019 As Platinum Sponsors
• Accellera Announces Public Source Code Repository
• Despite 38% Sales Decline, DRAM Expected to Remain Largest IC Market
• InAccel Accelerates XGboost and releases the IP core for FPGAs

Monday, July 29, 2019

• What's the best IP for machine learning workloads – CPU, GPU or NPU?
• Adesto Appoints Two New Board Members
• Wave Computing Signs New License Agreement with MediaTek
• Tortuga Logic's Radix Hardware Security Verification Solutions Licensed by Xilinx
• Apple to Buy Intel's Modem Business for $1 Billion

Sunday, July 28, 2019

• Rambus Reports Second Quarter 2019 Financial Results
• SRAM Challenges and MRAM Achievements
• TSMC to Boost Recruitment by More Than 3,000 New Hires
• Rambus to Acquire Northwest Logic, Extending Leadership in Interface IP
• Khronos Releases OpenXR 1.0 Specification Establishing a Foundation for the AR and VR Ecosystem
• SCALINX new ASIC design center in SOPHIA-ANTIPOLIS, France
• Alibaba Reveals 16-core RISC-V Chip

Friday, July 26, 2019

• Open Source Processors: Fact Or Fiction?