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Wednesday, July 24, 2019

• Q&A: Why it's time to focus on app security technologies for cars
• Semiconductor's Dinosaurs
• Allegro DVT Announces the Availability of the First AVS3 Compliance Test Suite
• New NVM Express, Inc. Specifications Bolster Cloud and Enterprise Advancements
• Xilinx Reports Record Revenues In Fiscal First Quarter 2020

Tuesday, July 23, 2019

• RISC-V's Role in Securing IoT-Connected Devices
• China's chipmakers could use RISC-V to reduce impact of US sanctions
• Qualcomm Introduces End-to-End Over-the-Air 5G mmWave Test Network in Europe to Drive 5G Innovation
• UMC Reports Second Quarter 2019 Results
• Is Apple planning to acquire Intel's mobile business?
• Adesto's AFE IP Licensed by GCT Semiconductor for Advanced 4G LTE Modem
• Taiwan Startups Build on Hardware Heritage with AI Focus
• Silvaco Partners with Incubator Silicon Power Technology to Accelerate Success of Semiconductor Startups
• Mixel Granted US Patent for its Innovative MIPI D-PHY RX+ Configuration

Monday, July 22, 2019

• When reset is the only option, what do you do if there is no button?
• IoT Nets Eye LoRa, NB-IoT
• Second Quarter 2019 Silicon Wafer Area Shipments Fall 2.2 Percent from First Quarter Levels
• Who's Who in the Exodus from China to Southeast Asia
• Pioneer Micro Technology Launches Silvaco PDK for its 0.35 um Silicon Foundry CMOS Process
• Samsung Begins Mass Production of Industry's First 12Gb LPDDR5 Mobile DRAM for Premium Smartphones
• Faraday Reports Second Quarter 2019 Financial Results 2Q19 Revenues NT$1.2 Billion, Up 11% QoQ
• Cadence Reports Second Quarter 2019 Financial Results

Sunday, July 21, 2019

• CEOs Diverge on Moore's Law
• Startup Runs AI in Novel SRAM
• TSMC Sees 5G Driving Strong Demand for 7nm
• Nvidia Poaches Intel Safety Guru
• Innovium Adopts the Cadence Innovus Implementation System for Its Highly Scalable Switch Silicon Family for Data Centers
• Gartner Says Worldwide Semiconductor Revenue to Decline 9.6% in 2019
• Cadence Introduces Conformal Litmus to Deliver Fastest Path to Full-Chip Constraints and CDC Signoff
• CEVA Acquires Hillcrest Labs Intelligent Sensor Technologies Business from InterDigital

Wednesday, July 17, 2019

• UltraSoC-led consortium secures £2m Innovate UK funding to develop cybersecurity solutions for connected and autonomous vehicles
• Arasan announces the immediate availability of its Ultra Low Power MIPI D-PHY IP Compliant to D-PHY Specification v1.20 for TSMC 22nm SoC Designs
• Synopsys and Ixia, a Keysight Business, Announce Collaboration to Enable Scalable Networking SoC Validation Solution
• UltraSoC-led consortium secures £2m Innovate UK funding to develop cybersecurity solutions for connected and autonomous vehicles
• DSP Concepts and CEVA Partner to Streamline Audio/Voice DSP Software Development for High-End Sound Applications
• InAccel releases world's first universal bitstream repository for FPGAs based on JFrog
• Samsung Begins Mass Production of Industry's First 12Gb LPDDR5 Mobile DRAM for Premium Smartphones
• Semi Content in Electronic Systems Forecast to Drop to 26.4% in 2019
• TSMC Reports Second Quarter EPS of NT$2.57

Tuesday, July 16, 2019

• Pioneer Micro Technology Launches Silvaco PDK for its 0.35 µm Silicon Foundry CMOS Process
• Cadence Delivers Portable Test and Stimulus Methodology and Library
• Xiaomi picks up 6% stake in chip designer VeriSilicon
• PCIe a Battlefield for Intel, Rivals
• StreamDSP Announces Major Update to 17.3 IP Core
• Lattice Semiconductor Delivers Flexible Connectivity for Industrial Vision Applications with New CrossLink Reference Design
• Pioneer Micro Technology Launches Silvaco PDK for its 0.35 µm Silicon Foundry CMOS Process

Monday, July 15, 2019

• Intel's Neuromorphic Loihi Processor Scales to 8M Neurons, 64 Cores
• CFX announces commercial availability of anti-fuse OTP technology on SMIC 55HV process
• SmartDV Adds DisplayPort 2.0 to its Portfolio of Verification IP
• NSITEXE Accelerates Delivery of Data Flow Processor IP for Automotive and Industrial Applications Using the Cadence Digital Design Full Flow
• Alphawave IP Announces Immediate Availability of Advanced PCIe Gen1-5 PHY on TSMC's 7nm process
• Arm Flexible Access gives chip designers the freedom to experiment and test before they invest
• New IP catalog from Terminus Circuits
• Attopsemi Technology Attended ChipEx2019 and Presented a Speech "I-fuse A Disruptive OTP (One-Time Programmable)"

Sunday, July 14, 2019

• RISC-V Foundation Launches Design Contest to Drive Security Innovation and Advance the Development of Secure RISC-V Solutions
• eSOL and Kalray extend their cooperation to address demanding needs of automotive, industrial and medical applications
• Accelerate Smart Embedded Vision Designs with Microchip's Expanding Low-Power FPGA Video and Image Processing Solutions
• Synopsys Awarded DARPA ERI Contract Extension for Analog/Mixed-Signal Emulation Technology Innovation
• WiSig Networks Adopts Palma Ceia SemiDesign for IoT Application Targeting Agricultural Environments
• Dolphin Integration and Maple Solutions announce their reseller partnership to support South Korean semiconductor companies