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Thursday, June 14, 2018

• RISC-V Day in Shanghai

Wednesday, June 13, 2018

• USB 3.0 – A Cost Effective High Bandwidth Solution for FPGA Host Interface
• SystemC Ecosystem gets boost with Accellera's new SystemC CCI 1.0 Standard
• Creonic's Quality Management System Achieves ISO 9001:2015 Certification
• Industrial Internet and Connected Vehicles Drive IoT Sales Through 20211
• Veea Acquires Virtuosys to Bolster Edge Computing Platform, Advancing IoT-Enabled Devices and Smart Applications
• Arm Ready to Sacrifice Profits for Long-Term IoT Growth
• Costs Dog PCIe Speed Gains
• Synopsys IC Validator Certified by Samsung Foundry for 7nm Signoff Physical Verification
• AI Startup Wave Computing To Buy MIPS
• Synopsys Fusion Technology Enables Lower Power, Smaller Area, and Higher Performance on Samsung Foundry 7LPP Process with EUV
• Industrial Internet and Connected Vehicles Drive IoT Sales Through 2021?
• Spin the Arm Virtual Prize Wheel at DAC 2018
• Layout Database File Control: The Missing Link

Tuesday, June 12, 2018

• Looking Ahead: What is Next for IoT
• Microsemi Collaborates with China Telecom to Deliver Optimized OTN Solution for 5G
• Chips&Media launches HEVC/H.264 combined codec IP (Single Core) optimized for UHD (4K, 60 FPS)
• Xpeedic's IRIS Certified for EM Simulation in GLOBALFOUNDRIES 22FDX Process
• AI Semiconductor Company Syntiant Demonstrates Analog Neural Network for Always-on Battery-powered Devices, Closes A Round Funding Led by Intel Capital
• Shanghai Huali Microelectronics Corporation (HLMC) Announces Collaboration with Adesto and CNE around RRAM Technology for RFID, Stand Alone NVM and Microcontroller Applications
• Arm Expands IoT Connectivity and Device Management Capabilities with Stream Technologies Acquisition

Monday, June 11, 2018

• 64-bit multi-cluster CPU IP is ISO 26262 & IEC 61508 compliant
• Synopsys Enables Secure App Development with Coverity Enhancements and Integrated Security Training Platform
• Silicon Catalyst Strengthens Leadership Team
• Baum Launches New Version of Power Modeling, Analysis Solutions for Hardware Design
• Semiconductor Equipment Record Spending Streak To Continue Through 2019
• Cambricon Licenses NetSpeed Fabric IP for Its Next-Gen Artificial Intelligence Products
• HunterSun Corporation Licenses AndesCore N1068A-S for Its HS6601 Single-Chip Bluetooth SoC Targeting Wireless Audio Applications
• National Instruments Adopts AccelerComm's 5G NR Polar IP
• Breker Verification Systems Unveils Next-Generation Trek5 with Fully Compliant Support for Accellera Portable Stimulus Standard
• Faraday Exhibits AI FPGA-to-ASIC Solution and IoT SoC Platform at DAC 2018
• CAST Adds JPEG-LS Decoder to Lossless Image Compression IP Core Suite
• Globalfoundries Cuts 5% of Workforce

Monday, June 11, 2018

• How Real is the Intellectual Property Revolution?

Monday, June 11, 2018

• FTC: Bar Rambus from enforcing patents

Sunday, June 10, 2018

• MIPS I6500-F First High Performance 64 Bit Multi-Cluster CPU IP to Receive ISO 26262 and LEC 61508 Certification
• Mentor Veloce hardware emulation platform now available on Amazon Web Services
• Fraunhofer's xHE-AAC Audio Codec Software Extends Native AAC Support In Android P For Better Quality At Low Bitrates

Thursday, June 7, 2018

• Imagination Technologies has announced two neural network accelerator cores
• PowerVR Series2NX neural network accelerator cores set the standard for performance and cost-efficiency
• Wally Rhines: Deep Learning Will Drive Next Wave of Chip Growth
• Credo Demonstrates Robust 200G & 400G Connectivity Product Solutions at Computex 2018
• Real Intent Awarded U.S. Patent for Methods and Systems for Correcting X-pessimism in Gate-level Simulation or Emulation
• TSMC May 2018 Revenue Report
• UMC Reports Sales for May 2018

Wednesday, June 6, 2018

• Arteris IP Announces CodaCache Standalone Last Level Cache
• Intento Design Cooperates with STMicroelectronics to Accelerate Analog Design and Migration of FD-SOI Chips at Functional Level
• Intento Design Cooperates with STMicroelectronics to Accelerate Analog Design and Migration of FD-SOI Chips at Functional Level
• AI Comes to ASICs in Data Centers
• Arm Sells Stake in China JV as EU Warns of Unfair Practice
• Cortus Asserts Intellectual Property Claims Against Microsemi, a Wholly Owned Subsidiary of Microchip Technology Inc. (Nasdaq: MCHP)
• Faraday Monthly Consolidated Sales Report - May 2018

Tuesday, June 5, 2018

• Embedded brain reading enables better human-robot interaction
• Cryptography-enabled MCU secures connected nodes
• Global Semiconductor Sales Increase 20 Percent Year-to-Year in April; Double-Digit Annual Growth Projected for 2018
• IEEE Announces Formation of Two New IEEE 802.11 Study Groups
• Hailo Raises $12.5 Million Series A Round to Develop Deep Learning Processor for Embedded AI Applications
• Sonics Partners With Synkom To Incorporate NoC and EPU IP Into Its Leading Semiconductor Design Services For Japan Customers
• Globalfoundries to add another NVM to FDSOI
• Samsung to introduce nanosheet transistors in 3nm node
• TSMC Shareholders Approve NT$8 Cash Dividend and Elect Board of Directors; Board of Directors Elect Mark Liu as Chairman and C.C. Wei as CEO and Vice Chairman
• GUC Monthly Sales Report - May 2018
• Mobiveil and Avery Design Systems Partner to Provide SoC Designers a Fully Verified and Compliant PCIe 5.0 IP Solution
• PLDA to Demonstrate Industry's First PCIe 4.0 Switch Platform with Multiple Downstream Ports during PCI-SIG DevCon 2018

Monday, June 4, 2018

• Synopsys Delivers AI-enhanced Digital Design Platform Bringing Artificial Intelligence to Design Implementation
• Sankalp Semiconductor to Exhibit at Design Automation Conference - 2018
• eSilicon revolutionizes machine learning ASIC platform (MLAP) market