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Friday, November 22, 2024

• Redefining Hearing Aids with Cadence DSPs

Thursday, November 21, 2024

• HPC customer engages Sondrel for high end chip design
• EU looks to change rules on technology transfer, patent pools

Wednesday, November 20, 2024

• Universal AI RISC-V processor does it all - CPU, GPU, DSP, FPGA
• Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
• TSMC drives A16, 3D process technology
• Solid Sands and VyperCore Collaborate to Ensure C/C++ Compliance in New Accelerator Chip Design
• SC24 Observations: China, Politics, RISC-V and CXL
• Optical Transmission Modulation Methods Advance
• GlobalFoundries awarded $1.5bn subsidy
• Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
• China's Huawei, SMIC 'to Ramp Production' of Newest AI Chip
• Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy

Tuesday, November 19, 2024

• Renesas Introduces Industry's First Complete Memory Interface Chipset Solutions for Second-Generation DDR5 Server MRDIMMs
• Nordic Simplifies Wireless Integration With New Low-Power SoCs
• Japan proposes $1.3bn investment in Rapidus
• GlobalFoundries and U.S. Department of Commerce Announce Award Agreement on CHIPS Act Funding for Essential Chip Manufacturing
• Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
• CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
• Capgemini, Mistral AI and Microsoft collaborate to further accelerate adoption of generative AI technologies
• Cadence Unveils Arm-Based System Chiplet

Monday, November 18, 2024

• Infineon and Siemens collaborate to bring AURIX TC4x to next generation software-defined vehicles
• Dnotitia Unveils the World's First Hardware-Accelerated Vector Database, Seahorse, at Super Computing 2024
• CAST Adds New SafeSPI Controller to its Functional Safety IP Core Product Line
• Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards

Sunday, November 17, 2024

• SLS Launches Industry-First USB 20Gbps Device IP Core
• QuickLogic to Showcase Advanced eFPGA Hard IP Solutions at Space Tech Expo Europe 2024
• NVIDIA Announces Omniverse Real-Time Physics Digital Twins With Industry Software Leaders
• Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
• Credo Completes First GHG Emissions Calculation, Strengthens Commitment to Environmental Sustainability
• Climate-friendly electricity is derived from ammonia

Friday, November 15, 2024

• Siemens Launches TIA Portal Version 20 Focused on Improved Performance
• RISC-V for HPC at SC24

Thursday, November 14, 2024

• TSMC grabs US$11 billion for Arizona fabs from US Chips Act
• Siemens presents next-generation AI-supported software for electronic system design
• QuickLogic to Showcase Advanced eFPGA Hard IP Solutions at Space Tech Expo Europe 2024
• Imec Chipset Alliance Aims to Expand AI to Cars
• Imec Chiplet Alliance Aims to Expand AI to Cars
• Grass Valley Adds JPEG XS Support to AMPP, Powered by intoPIX FastTicoXS Technology, Enhancing Cloud-Based Live Production
• Alphawave Semi Partners with PCISig, CXL Consortium, UCIe Consortium, Samtec and Lessengers to Showcase Advances in AI Connectivity at Supercomputing 2024
• AI Software Startup Moreh Partners with AI Semiconductor Company Tenstorrent to Challenge NVIDIA in AI Data Center Market

Wednesday, November 13, 2024

• Renesas' New R-Car SoC Supports Centralized Car Compute
• Renesas Unveils Industry's First Automotive Multi-Domain SoC Built with 3-nm Process Technology

Tuesday, November 12, 2024

• What RISC-V Means for the Future of Chip Development

Monday, November 11, 2024

• TI opens its first product distribution centre in Europe
• Silvaco Reports Third Quarter 2024 Financial Results
• Silicon Creations Celebrates Milestone with Delivery of 1,000th Production License for Fractional-N PLL
• LG and Tenstorrent Expand Partnership to Enhance AI Chip Capabilities
• intoPIX JPEG XS Powers Village Island's VICO-2L-XS for Cost-effective SDI/IP Conversion
• CHERI builds global chip security alliance
• CHERI Alliance Officially Launches, Adds Major Partners including Google, to Tackle Cybersecurity Threats at the Hardware Level
• Achronix and BigCat Wireless Collaborate to Deliver Unprecedented Power Efficiency and Performance for 5G/6G Wireless Applications
• Siemens extends Veloce hardware-assisted verification and validation with new Innexis shift-left software
• SEMIFIVE Collaborates with Synopsys to Develop Advanced Chiplet Platform for High-Performance Multi-Die Designs
• Samsung Reportedly Joins TSMC in Halting 7nm and Below AI Chip Supplies to China
• NanoXplore acquires Dolphin Design's ASIC business and strengthens its strategic position in aerospace
• lowRISC and SCI Semiconductor Partner to Create First CHERIoT Commercial Tapeout
• Kudelski IoT Launches Quantum-Resistant Security IP, Future-Proofing Semiconductors Against Emerging Quantum Threats
• intoPIX and Media Links: Powering Next-Generation IP Media Transport with JPEG XS at InterBEE 2024
• Arteris and MIPS Partner on High-Performance RISC-V SoCs for Automotive, Datacenter and Edge AI

Sunday, November 10, 2024

• Where the Future Begins: Samsung Showcases Pioneering Innovations for AI and Automotive Technologies at electronica 2024 in Munich
• Will Europe become the world's foundry for photonic chips?
• U.S. restricts TSMC's export of advanced chips to China
• Oriole Networks Selects EnSilica as ASIC Partner and Contract Award for Photonics Controller ASIC
• Oriole Networks Selects EnSilica as ASIC Partner and Contract Award for Photonics Controller ASIC
• Imagination DXS GPU officially certified as ASIL-B compliant
• Flex Logix Acquired By Analog Devices
• DMP Released Next-Generation AI Accelerator IP "ZIA A3000 V2" - Industry-leading PPA efficiency to propel the future of edge AI
• Delivering industry-leading solutions with Comprehensive Automotive Grade Silicon IP Portfolio with ISO 26262 and ASIL Certifications