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Friday, March 9, 2018

• UMC Reports Sales for February 2018

Thursday, March 8, 2018

• TSMC February 2018 Revenue Report
• Google sees quantum processor 'supremacy' at reach
• Intel, Microsft Partner on Machine Vision, AI

Wednesday, March 7, 2018

• NXP tackles edge processing with Arm-based processors
• Synopsys Collaborates with Samsung Foundry to Develop DesignWare IP for Samsung 8-nm FinFET Process
• Faraday Monthly Consolidated Sales Report - February 2018
• MIPI Alliance Expands Reach with New Automotive Working Group
• Kneron Announces Low Power AI Processors NPU IP Series with the Lowest Power Consumption: Less Than 5mW
• Arm Seminar: Upgrade to a Custom ASIC

Wednesday, March 7, 2018

• Rambus Initiates Accelerated Share Repurchase Program

Tuesday, March 6, 2018

• Arteris IP Supports Dream Chip Technologies Innovative Business Model for Automotive SoC Development
• Wave Computing Adopts Low Power MIPS 64-bit Multi-Threaded Core
• CEVA First to Deliver Bluetooth 5 Dual Mode IP
• Intrinsic ID and Technolution Awarded SBIR to Develop SEMIO IoT Security Platform
• M31 and Macroblock work together to deploy the global LED driver IC market
• GCT Semiconductor Licenses CEVA Bluetooth Low Energy IP for its LTE IoT SoC
• Imperas Appoints Kevin McDermott as Vice President of Marketing
• Arm delivers compelling visual experiences to the mainstream
• Are the Major DRAM Suppliers Stunting DRAM Demand?
• Chipus to offer Ultra-Low-Power Analog IP Solutions for SilTerra's IoT Platform
• US chipmaker GlobalFoundries asks China to probe TSMC

Tuesday, March 6, 2018

• Denali Announces State-of-the-Art GHz DDR PHY Technology

Monday, March 5, 2018

• Rambus Initiates Accelerated Share Repurchase Program
• January Semiconductor Sales Up 22.7 Percent Compared to Last Year
• Palma Ceia Closes Series B Funding, Internet of Things Connectivity to be Accelerated
• Synopsys Adds New Algorithms in DesignWare Security Protocol Accelerators to Increase Protection for IoT SoCs
• Silvaco Completes Acquisition of NanGate
• Broadcom Bid Gets U.S. Scrutiny
• ARM and embedded SIM
• Lattice launches 12Gbps wireless connector
• Samsung Electronics' C-Lab to Reveal New AI Projects at SXSW 2018
• Arm GPU Gets More AI Muscle
• Smaller chips, bigger opportunities: Where GlobalFoundries is going next
• GlobalFoundries gears up for the next generations of chip manufacturing

Sunday, March 4, 2018

• HCC Embedded Releases MISRA-Compliant Embedded Cryptography Suite and Manager
• GUC Monthly Sales Report - Feb 2018
• Trilinear Technologies and Avery Design Systems Team on DisplayPort IP Solutions
• Efinix Releases Trion Programmable Platform
• Barefoot Networks and Xilinx to Showcase Unprecedented Programmability and Visibility for 5G Networks
• Canaan-Creative employs Moortec's Temperature Sensor in their new ASIC aimed at HPC IC
• Microchip Technology To Acquire Microsemi
• Arm's John Ronco on IP for embedded
• 92 IC Wafer Fabs Closed or Repurposed From 2009-2017
• China Plans $31.5 Billion IC Industry Fund
• Analog-to-Digital Converter IP for IoT Designs
• EU puts 20 year span on 5G spectrum licences
• Embedded World: Cypress adds Arm secure firmware to PSoC6
• Qualcomm: Huawei 5G chip is too large for mobile terminals,

Thursday, March 1, 2018

• Ceva adds power DSP to Nokia 5G network
• Processing Power Driving Practicality of Machine Learning

Wednesday, February 28, 2018

• Imec and Cadence Tape Out Industry's First 3nm Test Chip
• Brite Semiconductor Releases Gen2 DDR LP PHY IP
• CEVA and Nokia Collaborate for 4.9G and 5G Technologies

Tuesday, February 27, 2018

• China's semiconductor firms catching up, but technology gap with foreign rivals still remains
• Worldwide Server Market Revenue Surges 26.4% in the Fourth Quarter Capping Off a Strong Second Half of 2017, According to IDC
• Truphone Brings New Integrated SIM Solution to Life With Synopsys ARC Secure IP Subsystem
• GloFo and eVaderis develop MRAM for MCU on 22nm FD-SOI
• Cadence, Imec Disclose 3-nm Effort
• Software-Based GPS Receiver from Galileo Satellite Navigation Now Available on Cadence Tensilica Fusion F1 DSP
• GOWIN Semiconductor selects PLDA XpressRICH3 Controller IP as the PCIe interface block in their FPGA product line
• S3 Semiconductors joins Arm Approved design partner program
• Trinamic Licenses Codasip's Bk3 RISC-V Processor for Next Generation Motion Control Applications
• GreenWaves Technologies Unveils GAP8, the Industry's Lowest Power IoT Application Processor, Enabling Groundbreaking Embedded Artificial Intelligence at the Very Edge

Tuesday, February 27, 2018

• Truechip Announces First Customer Shipment of PCIe Gen 5 and JESD204C Verification IP

Tuesday, February 27, 2018

• VeriSilicon Completes Series B Financing

Monday, February 26, 2018

• Neural Network Inference Engine IP Core Delivers >10 TeraOPS per Watt
• Maxim's Dynamic Speaker Management Technology Running on the CEVA-TeakLite-4 Ultra-Low-Power DSP Provides the Ultimate Sound Experience from Micro Speakers
• Neural Network Inference Engine IP Core Delivers >10 TeraOPS per Watt
• Northwest Logic's Expresso 4.0 Controller Core and Fidus Systems' Zynq UltraScale+ Platform demonstrates PCIe 4.0 Support
• RISC-V RV64GC High-Performance Extendable Platform Kit For Fast Linux Execution Released by Imperas
• OPENAIRINTERFACE software stack powering 5G use-cases exhibited at Mobile World Congress Barcelona
• Flex Logix Co-Founder Cheng Wang Awarded Interconnect Patent For Tiling of eFPGA Cores to Create Wide Range of Larger eFPGA Arrays
• Arteris IP FlexNoC Interconnect Licensed by AutoChips for Automotive SoC Development
• Single-Chip Custom Solutions for the IoT Edge
• Ashling and Imperas Partner to Extend the RISC-V Ecosystem
• GEO Semiconductor Selects Cadence Tensilica Vision P5 DSP for Their Most Advanced Automotive Smart Viewing Camera Processor
• Sonics Partners With Inomize To Enable Automotive Chip Design For ISO 26262 Standard
• GLOBALFOUNDRIES Strengthens 22FDX eMRAM Platform with eVaderis' Ultra-low Power MCU Reference Design
• AccelerComm and Achronix Enable Fast Time to Market with 5G Polar Code for Speedcore eFPGAs
• Blu Wireless Technology inside CCS self-organising mmWave access and backhaul solution
• Nuance Voice Activation Technology Now Available for CEVA-TeakLite Family, World's Lowest Power Audio/Voice DSPs

Sunday, February 25, 2018

• Qualcomm and Broadcom agree non-price-related conditions of takeover
• The hierarchical architecture of an embedded FPGA
• Sequans Introduces New NB-IoT Only Platform: Monarch N
• Inside Secure to Provide Secure Provisioning Solutions to ALi Corporation
• Metrics Partners with Avery to Expand Cloud Verification with Robust VIP Portfolio
• Synopsys Delivers Industry's First Complete UFS 3.0 IP Solution for High-Performance Embedded and Removable Storage
• IAR Systems enables high-performance machine learning based on latest neural network library from Arm
• CEVA Extends its IP Platforms for Bluetooth and Wi-Fi with RISC-V
• North American Semiconductor Equipment Industry Posts January 2018 Billings
• CEO interview: Flex Logix' Geoff Tate on licensing FPGA
• Magillem Partners with Imperas
• Avery Design Systems Announces SimXACT 5.0 for Improved X-Verification
• Huawei Enters Patent License Agreement for Fraunhofer IIS MPEG-4 Audio Patent Portfolio
• Dream Chip Technologies Demonstrates Superior Power Efficiency with Automotive Driver Assistance SoC on GLOBALFOUNDRIES 22FDX Technology
• Intel Ships Industry's First 58G PAM4-Capable FPGA Built for Multi-Terabit Network Infrastructure and NFV
• Lattice Releases Next-Generation FPGA Software for Development of Broad Market Low Power Embedded Applications
• CEVA and mPerpetuo Partner to Deliver Halide Support for CEVA Vision Processors
• Qualcomm Taps Samsung's 7nm EUV for 5G
• Goodix Announces Entry into the Growing NB-IoT Market with Its Acquisition of German-Based CommSolid
• Ceragon License CEVA DSPs for Full 5G Wireless Backhaul
• RISC-V Gains Its Footing
• AMIQ EDA Announces its Design and Verification Tools Eclipse IDE Supports Cadence Perspec System Verifier using System Level Notation