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Sunday, October 22, 2017

• Silvaco Introduces Arm Cortex M0-based I3C Sensor Subsystem
• Guardtime and Intrinsic ID Awarded Dutch Government Contract for Distributed Energy Marketplace via a Decentralized Trading Platform
• Rambus Reports Third Quarter 2017 Financial Results
• Menta Joins GLOBALFOUNDRIES' FDXcelerator Partner Program
• TSMC head optimistic about future of semiconductor market
• 90% Reduction in power consumption for RFID chips with Dolphin Integration's SESAME eLC standard cell library
• Lowering Barriers to Entry for ASICs
• RAPID SOC PROOF-OF-CONCEPT FOR ZERO COST

Friday, October 20, 2017

• OVH launches Acceleration-as-a-Service Leveraging the New Intel Programmable Acceleration Card and App Store from FPGA Acceleration Partner Accelize

Thursday, October 19, 2017

• QuickLogic to Showcase Latest eFPGA and Sensor Processing Solutions at Arm TechCon 2017
• Arm and Hackster.io announce the Arm Innovator Program

Thursday, October 19, 2017

• M31 Technology and Corigine have launched the world's first USB-IF certified 28 nm Superspeed+ USB 3.1 Gen 2 IP Solution

Wednesday, October 18, 2017

• ArterisIP Acquires iNoCs Software and Associated Intellectual Property Rights
• Rambus Validates Interoperability of DDR4 High-performance Memory IP Solution for Arm-based Datacenter Systems
• Xylon Presents New Modular Video Logger
• Xylon Showcases the New Modular Video Data Logger at Automotive Testing Expo North America 2017
• Microsemi Launches Mi-V Ecosystem to Accelerate Adoption of RISC-V
• Inside Secure brings to market industry's only complete and fully-certified cloud-based mobile payment solution
• CEVA and Cyberon Partner for Ultra-low Power Always-listening Voice Activation Solution
• IC Insights Raises 2017 IC Market Forecast to +22%
• TSMC Reports Third Quarter EPS of NT$3.47
• Microsemi's Lowest Power, Cost-Optimized Mid-Range PolarFire FPGAs Achieve Key Milestone by Passing PCI SIG's PCIe Endpoint Compliance Suites
• M31 Technology and Corigine have launched the world's first USB-IF certified 28 nm Superspeed+ USB 3.1 Gen 2 IP Solution
• ST's low-power fabs are just what Europe needs

Wednesday, October 18, 2017

• Open-Silicon to Demonstrate its High Bandwidth Memory (HBM2) IP Subsystem Solution for High Performance Computing and Networking Applications and Showcase its IoT Gateway SoC Reference Design for Smart City Applications at ARM TechCon 2017

Tuesday, October 17, 2017

• China Semiconductor Fab Equipment Spending Forecasted to Over Than $12 Billion
• CEVA and Brodmann17 Partner to Deliver 20 Times more AI Performance for Edge Devices
• Samsung Secures IoT Node-to-Cloud
• Synopsys and NXP Extend Multiyear Automotive Center of Excellence Collaboration for NXP S32 Automotive Processing Platform
• Allegro DVT Releases a New Generation of Encoder IPs
• Corigine Unveils First Certified SuperSpeed+ USB 3.1 Gen 2 IP With M31 28nm PHY
• Samsung Completes Qualification of 8nm LPP Process

Tuesday, October 17, 2017

• MIPI Alliance Announces Milestones in Membership Growth and Industry Influence

Tuesday, October 17, 2017

• Dr. Haijun Zhao, Dr. Liang Mong Song Appointed as SMIC Co-CEO and Executive Director

Tuesday, October 17, 2017

• Synopsys and GLOBALFOUNDRIES Collaborate to Develop DesignWare IP for 22FDX Process

Tuesday, October 17, 2017

• New MIPI Alliance Group Collaborates with Automotive Industry Experts to Address Interface Specifications for Automotive Applications

Tuesday, October 17, 2017

• NovaSparks introduces "U.S. Equities in a Box" solution

Monday, October 16, 2017

• CAST Introduces GZIP Accelerator Through New Intel FPGA Data Center Acceleration Ecosystem
• Gartner Says Worldwide Device Shipments Will Increase 2.0 Percent in 2018, Reaching Highest Year-Over-Year Growth Since 2015
• CENTRI Announces Immediate Availability of IoT Advanced Security for the Arm Mbed IoT Device Platform
• Montage Technology Licenses Allegro DVT's Latest Multi-Format Video Encoder IP for Next Generation Set-Top Box Chips
• CEVA and LG Electronics Partner for Smart 3D Camera Solution
• Intel to Battle in FPGA-as-a-Service Race
• Achronix Speedcore Custom Blocks Supercharge Data Acceleration Systems
• Synopsys Expands DesignWare IP Portfolio with Acquisition of Sidense Corporation
• Mixel's MIPI C-PHY/D-PHY Combo IP is Silicon-Proven in Multiple Nodes
• sureCore Joins GLOBALFOUNDRIES FDXcelerator Partner Program
• REFLEX CES Partners with NOLAM EMBEDDED SYTEMS to Provide Integrated CANbus IP Core Solutions on FPGA COTS Boards
• CAST Introduces GZIP Accelerator Through New Intel FPGA Data Center Acceleration Ecosystem

Monday, October 16, 2017

• Moortec to exhibit their embedded In-Chip Monitoring Subsystem IP at the 2017 ARM TechCon in Santa Clara

Monday, October 16, 2017

• Accellera Systems Initiative advances the SystemC ecosystem with a new core language library

Monday, October 16, 2017

• SiFive Joins TSMC IP Alliance Program

Monday, October 16, 2017

• Thalia DA attracts fresh investment as semiconductor industry recognizes analog IP reuse challenge

Monday, October 16, 2017

• TSMC Senior Vice President Dr. Stephen Tso to Retire

Sunday, October 15, 2017

• 赵海军、梁孟松博士受任中芯国际联合首席执行官兼执行董事
• Codasip Hires IP Industry Veteran Chris Jones as Vice President of Marketing
• Open-Silicon to demonstrate its IoT Edge SoC Platform Solution, IoT Gateway SoC Reference Design and Comprehensive HBM2 IP Subsystem Solution for 2.5D ASICs in TSMC 16nm FF+ at Arm TechCon 2017
• NXP Announces New Automotive Processing Platform that Brings Future Vehicles to Market Faster
• Wafer Shipments Forecast to Increase in 2017, 2018 and 2019
• Dolphin Integration Joins GlobalFoundries FDXcelerator Program to Provide Breakthrough Fabric IP

Thursday, October 12, 2017

• 意法半导体(ST)将其独有的开发生态环境与阿里AliOS操作系统完美结合
• Intel FPGAs Power Acceleration-as-a-Service for Alibaba Cloud
• IC Makers Maximize 300mm, 200mm Wafer Capacity

Thursday, October 12, 2017

• GLOBALFOUNDRIES Introduces New Automotive Platform to Fuel Tomorrow's Connected Car

Wednesday, October 11, 2017

• CEO interview: S3 Semi ready for custom opportunity
• Xilinx Selected by Alibaba Cloud for Next-Gen FPGA Cloud Acceleration
• Rambus Delivers High-Speed SerDes Interface Solutions on GLOBALFOUNDRIES FX-14 ASIC Platform for Data Center and Enterprise
• Cadence Announces Digital and Signoff Flow Support for Body-Bias Interpolation for GLOBALFOUNDRIES 22FDX Process Technology
• 本周新闻概述
• Imec and Analog Devices sign strategic research partnership for development of next-generation IoT devices
• S3 Semiconductors selected to advance Satellite Transceiver Technology in ESA ARTES Partner Programme
• Gartner Says Worldwide Semiconductor Revenue to Reach $411 Billion in 2017

Tuesday, October 10, 2017

• Synopsys与GLOBALFOUNDRIES合作开发22 FDX®工艺的DesignWare IP
• Hiroshima University Research Team Accelerates the Development of a Computer-Aided Medical Diagnosis System with Cadence Tensilica Vision P6 DSP Core and Protium S1 FPGA-Based Prototyping Platform
• Taiwan Hits Qualcomm With $774 Million Fine
• Sankalp Semiconductor receives investment from Stakeboat Capital Fund
• Lauterbach debugger targets 64-bit Arm and Intel chips in cars
• Cadence Achieves TUV SUD's First Comprehensive "Fit for Purpose - TCL1" Certification in Support of Automotive ISO 26262 Standard
• QuickLogic Partners with AcconSys to Expand eFPGA Design Activity in China
• Mobiveil Announces 25xN RapidIO Specification 4.1 (25G) Digital Controller IP for Next-Generation Wireless Networking, High-Performance Computing Applications
• ST to build two new 300mm fabs

Tuesday, October 10, 2017

• Teradyne Standardizes on Cadence Xcelium Parallel Logic Simulator

Tuesday, October 10, 2017

• BaySand Makes It Even Easier to Access Arm-based Custom ASIC, Using Arm DesignStart

Tuesday, October 10, 2017

• Report: TSMC's 3nm Fab Could Cost $20 Billion