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Thursday, October 24, 2024

• Synopsys' $34 Billion Ansys Deal Gets UK Antitrust Scrutiny
• Silvaco Inc. Achieves ISO 9001 Certification for Comprehensive Suite of TCAD, EDA, and IP Products
• Next generation AI chip design exploration at imec UK
• Empowering a sustainable AI revolution

Wednesday, October 23, 2024

• The Role of Edge Computing in Evolving Software-Defined Vehicle Architectures
• SCI Semiconductor announces Global-First CHERI enabled devices and Early Access Program
• Mature Process Capacity to Grow 6% in 2025; Chinese Foundries Lead Expansion
• Intel-Samsung foundry collaboration
• IC'Alps obtains Common Criteria site certification with Tiempo Secure as sponsor
• Arm puts Qualcomm on notice of cancellation of its licence

Tuesday, October 22, 2024

• Silicon IP Provider, Chips&Media Unveils New Multi Video Codec IP, WAVE6 Gen2+
• RISC-V reaches milestone with RVA23 profile ratification
• M31 Once Again Ranked Among Forbes' "Asia 200 Best Under a Billion" List
• Logic Design Solutions launches an EXFAT IP Soft Core for NVMe Host
• Google Reportedly Switching To TSMC 3nm 'N3E' Process For Its Tensor G5, Tensor G6 To Be Mass Produced On The More Advanced 'N3P' Technology
• GlobalFoundries and NXP to Deliver Next-Generation 22FDX Solutions for Automotive, IoT and Smart Mobile
• Fraunhofer ISE opens battery research centre in Freiburg
• First CHERI RISC-V embedded chip and Early Access Programme
• Celestial AI Acquires Rockley Photonics Patent Portfolio, Strengthening Photonic Fabric IP

Monday, October 21, 2024

• White Paper - CANsec: Security for the Third Generation of the CAN Bus
• VeriSilicon's DeWarp Processing IP DW200-FS achieved ISO 26262 ASIL B certification
• RISC-V Announces Ratification of the RVA23 Profile Standard
• MosChip Technologies joins Renesas RZ Partner Ecosystem as AI/ML Design Partner
• Logic Fruit Technologies Welcomes Mr. Gurudutt (GD) Bansal as Senior Vice President Engineering
• Logic Design Solutions launches an EXFAT IP Soft Core for NVMe Host Targeting embedded recorder systems
• Keysight collaborates with Siemens EDA enabling next generation of wireless design
• IoT providers need to deliver more than connectivity, says report
• Intel Explores Foundry Alliance with Samsung in High-Level Talks
• Improved materials for microchip interconnections
• Fractile Licenses Andes Technology's RISC-V Vector Processor as It Builds Radical New Chip to Accelerate AI Inference
• DeepComputing and Andes Technology Partner to Develop the WorldÂ’s First RISC-V AI PC with 7nm QiLai SoC, Featuring Ubuntu Desktop
• DeepComputing and Andes Technology Partner to Develop the World's First RISC-V AI PC with 7nm QiLai SoC, Featuring Ubuntu Desktop
• China's first 3nm SoC by Xiaomi marks a seven-year gap since its last launch, likely manufactured by TSMC
• Andes Technology Unveils the D45-SE RISC-V Processor Targeting ASIL-D Certification
• Alphawave Semi Q3 2024 Trading and Business Update

Monday, October 21, 2024

• Andes Announces the AndesCoreâ„¢ 46-Series Family and the 3rd generation Vector Processor AX46MPV with Matrix Extension

Monday, October 21, 2024

• EnSilica plc - Award of £2 million Controller ASIC Design Services Contract

Sunday, October 20, 2024

• The pace quickens for cryptography
• SiFive HiFive Premier P550 Development Boards Now Shipping
• EnSilica plc - Award of £2 million Controller ASIC Design Services Contract
• Codasip enables secure Linux by donating CHERI RISC-V SDK to the CHERI Alliance
• Arteris and SiFive Deliver Pre-verified Solution for the Datacenter Market
• Andes Announces the AndesCore™ AX66 supporting RVA23, Multi-cluster, Hypervisor and Android
• Andes Announces the AndesCore™ 46-Series Family and the 3rd generation Vector Processor AX46MPV with Matrix Extension

Friday, October 18, 2024

• Arteris Evolves Its Network-on-Chip Tiling to Accelerate AI Designs

Friday, October 18, 2024

• Synopsys DesignWare USB 2.0 and Ethernet IP Enables First-Pass Silicon Success for STMicroelectronics

Friday, October 18, 2024

• Imagination Technologies announces OpenVG 1.1 conformance for POWERVR SGX range of scalable graphics cores

Thursday, October 17, 2024

• TSMC Reports Third Quarter EPS of NT$12.54
• The role of RISC-V in the European Processor Initiative - Interview with Roger Espasa

Thursday, October 17, 2024

• Outlook 2025: Embracing the chiplet journey

Wednesday, October 16, 2024

• Thalia adds analog and mixed-signal IP reuse to Siemens' Cre8Ventures Digital Twin Marketplace
• Samsung offers first 24Gb GDDR7 DRAM for AI computing
• Rebellions Builds Chiplet Roadmap, Merges with Sapeon
• Ex-Samsung executive wants a slice of self-driving car market
• EnSilica - Design and Supply contract award for a controller ASIC for automotive and industrial markets

Tuesday, October 15, 2024

• Successful tape out of Chip Interfaces' JESD204D IP by a tier 1 semiconductor company
• Samsung Foundry Pushes Up The Race Against TSMC In "Process Superiority", Starts Prepping 2nm & 1.4nm Production Lines
• Rebellions partners with Arm on AI computing chiplet Techs
• Intel and AMD form x86 Ecosystem Advisory Group
• Efabless Goes the Custom Route for Edge ML
• ADTechnology Partners with Arm, Samsung Foundry, and Rebellions on AI CPU Chiplet Platform

Monday, October 14, 2024

• Weebit Nano expands global sales infrastructure to support increased demand
• Silvaco Announces Preliminary Unaudited Revenue for Q3 and Updates Full Year 2024
• Rambus Unveils Industry-First Complete Chipsets for Next-Generation DDR5 MRDIMMs and RDIMMs to Deliver Breakthrough Performance for Data Center and AI
• eMemory Join Forces with Siemens on Groundbreaking SRAM Repair Toolset: Pre-integrated Tessent MemoryBIST with NeoFuse OTP
• Codasip unveils versatile automotive-grade embedded RISC-V core
• CEA-Leti Launches OpenTRNG, an Open-Source Project For True Random Number Generators Using Ring-Oscillator-Based Architectures
• CAST Partners with KiviCore for Post-Quantum Cryptography
• Cadence Announces Fem.AI Alliance to Lead Gender Equity Revolution in the AI Workforce
• Axiomise 7th birthday - we are proud to be at DVCon Europe
• Arteris Network-on-Chip Tiling Innovation Accelerates Semiconductor Designs for AI Applications
• Arm Total Design Ignites Growing Ecosystem of Arm-based Silicon for a Sustainable AI Datacenter
• AI and Semiconductors: A Symbiotic Relationship
• Agile Analog announces MoU to support new Southern Taiwan IC Design Industry

Sunday, October 13, 2024

• TSMC "already planning" for more European fabs
• Supercharging Automotive Production Line With AI-Powered Manufacturing
• Siemens Updates Simcenter Testlab for Advanced Manufacturers
• SEMIFIVE Extends Partnership with Arm to Advance AI and HPC SoC Platforms
• SEMIFIVE Concluded Mass Production Contract for AI Chip with HyperAccel
• Samsung's Next Move? Early HBM4 Mass-production and 2nm Foundry Solutions Could Be the Cure
• Kernkonzept and Lauterbach Make Virtualized RISC-V Systems Possible
• Exclusive Interview: Antti Rauhala Discusses CoreHW's CHW3021 Radio Front-End IC
• DisplayPort Rx PHY and Controller IP Cores in multiple Leading Technology Nodes for Next-Generation Video SoCs
• Credo Announces PCI Express 6 /7, Compute Express Link CXL 3.x Retimers, and AEC PCI Express Product Line at OCP Summit 2024