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Friday, September 22, 2017

• North American Semiconductor Equipment Industry Posts August 2017 Billings

Thursday, September 21, 2017

• Imagination Technologies: Sale of MIPS and update on Formal Sale Process
• 利用硬件安全模块将安全性置入你的系统级芯片（SoC）

Thursday, September 21, 2017

• ST, ARM challenged by TI strategic shift, says analyst

Thursday, September 21, 2017

• CAST Offers H.264 High-Profile Encoder IP Core for FPGAs and ASICs

Thursday, September 21, 2017

• Imagination's new PowerVR GPUs enable chip companies and OEMs to create the best possible user experience in cost-sensitive devices

Thursday, September 21, 2017

• Sondrel Expands into India

Thursday, September 21, 2017

• Top Women Execs Join NetSpeed Boards

Wednesday, September 20, 2017

• Globalfoundries Reportedly Asks EU to Probe TSMC
• Mentor Precision Synthesis announces support for the eFPGA fabric in Silicon Mobility's OLEA automotive IC
• Imagination reveals PowerVR Neural Network Accelerator (NNA) with 2x the performance and half the bandwidth of nearest competitor

Wednesday, September 20, 2017

• Cadence Tools and Flows Achieve Production-Ready Certification for TSMC's 12FFC Process

Wednesday, September 20, 2017

• GLOBALFOUNDRIES and Soitec Enter Into Long-term Supply Agreement on FD-SOI Wafers

Tuesday, September 19, 2017

• 最新Cadence Allegro DesignTrue DFM技术全面加速产品开发及上市流程
• MIPI Alliance to Host DevCon Event in the Heart of Taiwan's High-Tech Sector: Hsinchu City
• videantis receives growth financing from eCAPITAL to accelerate market penetration in embedded vision and autonomous driving
• Rambus Announces Industry's First Functional Silicon of Server DIMM Buffer Chipset Targeted for Next-generation DDR5
• Leading-Edge Paves the Way For Pure-Play Foundry Growth
• GLOBALFOUNDRIES Introduces New 12nm FinFET Technology for High-Performance Applications
• GLOBALFOUNDRIES Announces Availability of Embedded MRAM on Leading 22FDX FD-SOI Platform
• Synopsys Design Platform Certified by GLOBALFOUNDRIES for 22nm FD-SOI Process Technology

Tuesday, September 19, 2017

• Lattice Semiconductor's iCE40 FPGA Enables Low Latency and Concurrent Sensor Processing in SteamVR Tracking

Tuesday, September 19, 2017

• Synopsys Strengthens Design-Technology Co-Optimization Solution with Acquisition of QuantumWise

Tuesday, September 19, 2017

• SEGGER Adds Support for SiFive's Coreplex IP to Its Industry Leading J-Link Debug Probe

Tuesday, September 19, 2017

• AFuzion and HDL Design House Joint Webinar: Optimizing DO-254: October 4, 2017, 4 pm CEST

Monday, September 18, 2017

• The U.S., China and the Chip Industry
• CommSolid is now a Member of 3GPP and ETSI
• CoreHW accelerates growth - Panostaja invests in CoreHW by purchasing a majority shareholding
• Intel and Waymo team up on driverless cars
• Synopsys' New ARC Secure IP Subsystem Addresses Security Threats in Embedded SIM and Other High-Value Embedded Applications
• ArterisIP Ncore Cache Coherent Interconnect and Resilience Package Licensed by NXP
• Cadence Full-Flow Digital and Signoff Tools and Custom/Analog Tools Certified and Enabled for Intel 22FFL Process Technology
• Intel Technology and Manufacturing Day in China Showcases 10 nm Updates, FPGA Progress and Industry's First 64-Layer 3D NAND for Data Center
• Intel Custom Foundry Certifies Synopsys Design Platform for Intel's 22nm FinFET Low Power Process Technology
• Embedded FPGAs from Menta qualified for GLOBALFOUNDRIES' Advanced 14nm FinFET and 32nm SOI Process Technologies

Monday, September 18, 2017

• Conversant Announces Semiconductor Memory Patent License Agreement With Toshiba

Monday, September 18, 2017

• SMIC, Brite Semiconductor and Synopsys Collaborate to Deliver Low Power Platform for the Internet of Things

Sunday, September 17, 2017

• Mentor emulation platform receives safety certificate
• Cellular Puts IoT on Speed Dial
• CEVA Named in Fortune's 2017 100 Fastest-Growing Companies List
• TSMC Recognizes Synopsys with Four Partner Awards at the Open Innovation Platform Forum Event
• Cadence Recognized with Three TSMC Partner of the Year Awards
• 莱迪思半导体iCE40 FPGA为SteamVR跟踪平台实现低延迟的同步传感器数据处理功能
• Synopsys' New ARC IoT Development Kit Accelerates Software Development for Sensor Fusion, Voice Recognition and Face Detection Designs
• 灿芯半导体、中芯国际及Synopsys合作开发物联网低功耗平台

Friday, September 15, 2017

• Nevion integrates TICO lightweight compression into its Virtuoso product line.

Friday, September 15, 2017

• Xilinx Software Defined Development Environment for Data Center Acceleration Now Available on Amazon Web Services

Thursday, September 14, 2017

• iPhone X chip shows problems of Imagination
• Synopsys成功完成台积公司7纳米FinFET制程IP组合的投片
• SJSemi and Qualcomm Jointly Announce Qualification of 10nm Ultra-high Density Wafer Bumping Technology

Thursday, September 14, 2017

• Credo Receives Coveted TSMC 2017 Open Innovation Platform® Partner of the Year Specialty Technology IP Award

Thursday, September 14, 2017

• HCC Embedded's Extensive Suite of Advanced Middleware Now Available for Xilinx Zynq-7000 SoCs

Thursday, September 14, 2017

• Configurable VLIW core boosts energy efficiency for long battery life

Thursday, September 14, 2017

• PathPartner Will Be at IBC 2017, Showcasing 4K HEVC Encoder and Decoder Solutions

Thursday, September 14, 2017

• Soitec launches FD-SOI pilot line in Singapore

Thursday, September 14, 2017

• Sencore adopts intoPIX JPEG2000 Ultra Low Latency technology

Wednesday, September 13, 2017

• Chip Consolidation Nearly Over, Analyst Says
• China condemns protectionism after Lattice deal blocked
• eMemory Receives 2017 TSMC IP Partner Award
• Flex Logix Wins TSMC Open Innovation Platform Partner Of The Year Award 2017
• TSMC Updates its Silicon Menu

Wednesday, September 13, 2017

• Credo Demonstrates Single-Lane 112G and 56G PAM4 SerDes IP Solutions at TSMC 2017 OIP Ecosystem Forum

Wednesday, September 13, 2017

• UltraSoC expands to address embedded analytics market opportunity

Wednesday, September 13, 2017

• Moortec to exhibit their embedded In-Chip Monitoring Subsystem IP at the 2017 Design & Reuse IP SoC Event in Shanghai

Wednesday, September 13, 2017

• Packet Partners with Arm to Accelerate Adoption of Armv8-A for Datacenter Workloads

Tuesday, September 12, 2017

• Lattice Semiconductor and Canyon Bridge Capital Partners, LLC Announce Termination of Merger Agreement Following Decision from President Trump
• eSilicon tapes out deep learning ASIC
• Cadence Introduces the Conformal Smart Logic Equivalence Checker
• Arrows all-in-one IoT platform has Renesas Synergy MCU and Bosch sensors
• Synopsys and Alango Technologies Introduce Voice Enhancement Package Optimized for DesignWare ARC Data Fusion IP Subsystem
• PLDA Further Strengthen Partner Ecosystem, Unveils Comprehensive PCIe PHY and Controller integrated Solutions, to be Presented at IP-SoC China 2017

Tuesday, September 12, 2017

• BrainChip Introduces World's First Commercial Hardware Acceleration of Neuromorphic Computing

Tuesday, September 12, 2017

• Analog Bits to Demonstrate New High Performance and Ultra-Low Power SERDES IP at TSMC Open Innovation Platform Ecosystem Forum

Tuesday, September 12, 2017

• NGCodec and Tiledmedia to Show Cloud Hardware-Accelerated Low-Latency HEVC VR360 Streaming Solution at IBC 2017

Tuesday, September 12, 2017

• ArterisIP FlexNoC Interconnect Licensed by Renesas

Monday, September 11, 2017

• Fab Equipment Spending Breaking Industry Records
• NXP Tackles V2X, Unveils 'Vision' Roadmap
• Codeplay adds support to Renesas R-Car platform
• Sidense and Intellitech collaborate on Electronic Chip IDs, anti-counterfeiting and semiconductor security for Secure Supply Chain Enablement
• EEMBC Benchmark Verifies Energy Cost of Integrated Microcontroller Peripherals
• Mobiveil Inc. and Crossbar Inc. Announce Partnership to Apply Mobiveil's NVMe Solid State Drive IP to Crossbar's ReRAM IP blocks
• Synopsys and TSMC Collaborate to Develop DesignWare Foundation IP for Low-Power TSMC 40-nm eFlash Processes
• Samsung Strengthens Advanced Foundry Portfolio With New 11nm LPP and 7nm LPP With EUV Technology
• Nextchip License CEVA Imaging and Vision Platform for ADAS Vision System
• Open-Silicon Completes Successful Silicon Validation of High Bandwidth Memory (HBM2) IP Subsystem Solution
• QuickLogic First to Offer eFPGA Technology on SMIC 40nm Low Leakage Process
• Creonic Joins Consortium to Develop FEC Codes for Beyond-5G Tb/s Use Cases
• Xilinx、Arm、Cadence和台积共同宣布构建首款基于7纳米工艺的CCIX测试芯片

Monday, September 11, 2017

• Shanghai Zhaoxin Semiconductor Co., Ltd. licenses Dolphin Integration ultra dense audio DAC for its next generation of Set Top Box

Monday, September 11, 2017

• Synopsys IC Compiler II Certified for TSMC's Advanced 7-nm FinFET Plus Node

Monday, September 11, 2017

• Xilinx, Arm, Cadence, and TSMC Announce World's First CCIX Silicon Demonstration Vehicle in 7nm Process Technology

Monday, September 11, 2017

• UPMEM Announces the First Processing In-Memory Chip Accelerating Big Data Applications

Monday, September 11, 2017

• Semiconductor Industry Records Best Second Quarter in Three Years, IHS Markit Says

Monday, September 11, 2017

• True Circuits Attends the TSMC 2017 NA OIP Ecosystem Forum

Sunday, September 10, 2017

• S3 adds custom chip business model
• Inside Secure Announces Successful Fundraising of 16M Euros
• PathPartner Technology and Accelize Announce Availability of HEVC / H.265 FPGA Decoder for QuickPlay Development Platform
• Image Matters Delivers Disruptive Innovation with PathPartner
• PLDA Announces Industry's First Controller for FPGA supporting PCIe 4.0 v0.9, Allowing immediate PCIe 4.0 implementation into FPGAs
• SEMI Reports Second Quarter 2017 Worldwide Semiconductor Equipment Figures; Record Quarterly Billings of $14.1 Billion
• Cadence Collaborates with TSMC to Advance 7nm FinFET Plus Design Innovation
• Synopsys' IC Compiler II Completes Certification for TSMC's 12-nm Process Technology
• Synopsys Successfully Tapes Out Broad IP Portfolio for TSMC 7-nm FinFET Process
• Silicon Creations Celebrates 100th Tape-Out of Its PLL in TSMC 28nm Process Technology