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Saturday, June 29, 2024

• EDA Companies Unite With Samsung for AI and 3D IC Technology

Thursday, June 27, 2024

• STMicroelectronics restructures for the AI age
• RISC-V Summit Europe News - Processor IP, Verification Tools, and More

Wednesday, June 26, 2024

• Rambus offers DDR5 server PMICs to address AI workloads
• Frontgrade Gaisler Awarded ESA Contract to Qualify Spacecraft Avionics Microcontroller for Flight
• Faraday Joins Intel Foundry Accelerator Design Services Alliance to Target Advanced Applications
• Crafting a Silicon Lifecycle Management Strategy for HPC and Data Centers
• Axelera AI raises $68m for data centre push
• All systems go for 7nm FDSOI

Wednesday, June 26, 2024

• Lattice Introduces New Secure Control FPGA Family with Advanced Crypto-Agility and Hardware Root of Trust

Tuesday, June 25, 2024

• M31 Debuts at the North American Design Automation Conference, Showcasing IP Solutions for Advanced Processes
• Cadence Expands System IP Portfolio with Network on Chip to Optimize Electronic System Connectivity
• Tenstorrent To Offer AI Workstation For Developers
• FortifyIQ Introduces FortiPKA-RISC-V: A Breakthrough in Public Key Cryptography Acceleration

Tuesday, June 25, 2024

• Cypress Delivers Media Transfer Protocol Reference Design For Portable Media Players

Tuesday, June 25, 2024

• Europe invests 830 million euros to build FAMES FD-SOI pilot line to achieve 7nm with planar CMOS
• Intel's Latest FinFET Is Key to Its Foundry Plans

Monday, June 24, 2024

• X-Silicon Introduces the World's First Vulkan Driver Implementation for RISC-V, Enabling an entire Ecosystem of 3D Graphics, AI and Compute for Low-Power, Mobile, Edge and IOT Devices
• SiFive Announces 4th Generation of Popular Essential Product Line to Spur Innovation Across Embedded Applications
• Comcores Unveils Industry-First MAC Privacy Protection IP for Enhanced Ethernet Security
• ESWIN Computing Pairs SiFive CPU, Imagination GPU and In House NPU in Latest RISC-V Edge Computing SoC
• Enosemi announces availability of C-band-compatible electronic-photonic design IP
• Siemens and Intel Foundry collaborate to deliver new tools certifications and EMIB/3D-IC innovation
• Synopsys Accelerates Chip Innovation with Production-Ready Multi-Die Reference Flow for Intel Foundry
• Siemens introduces Innovator3D IC - a comprehensive multiphysics cockpit for 3D IC design, verification and manufacturing
• CEA-Leti Announces Launch of FAMES Pilot Line As Part of EU Chips Act Initiative
• Siemens delivers a major leap toward mainstream 3D-IC adoption with new Calibre 3DThermal
• Semidynamics releases Tensor Unit efficiency data for its new All-In-One AI IP

Monday, June 24, 2024

• True Circuits Introduces the JSPICEâ„¢ Design Environment (JDEâ„¢) at the Design Automation Conference

Monday, June 24, 2024

• EDA vendors put Intel EMIB interconnect in design flows for 3D ICs
• Siemens gets certification for Solido SPICE on Intel nodes, and adds EMIB
• Efabless Empowers 40 Commercial Companies to Design Chips
• Can Semiconductor Chips be Recycled?

Sunday, June 23, 2024

• SignatureIP Makes Network-on-Chip (NoC) Design Widely Accessible with Cloud-Based iNoCulatorâ„¢ Platform
• Baya Systems and Blue Cheetah Partner to Deliver Chiplet Interconnect Solutions
• Siemens delivers AI- accelerated verification for analog, mixed-signal, RF, memory, library IP and 3D IC designs in Solido Simulation Suite
• Semiwise, sureCore, and Cadence Showcase Breakthrough in Cryogenic CMOS Circuit Development for Quantum Computing and Energy-Efficient Data Centers
• Crypto Quantique, ZARIOT and Kigen unveil quantum-safe hardware root-of-trust for cellular IoT
• Ceva Extends its Smart Edge IP Leadership, Adding New TinyML Optimized NPUs for AIoT Devices to Enable Edge AI Everywhere
• Flex Logix Celebrates 10 Years of Success and Innovation
• T2M-IP Announces Silicon-Proven MIPI D-PHY v2.5 Tx and DSI-2 Tx Controller Low-Power, Cost-Effective IP Cores Solutions for Advanced SoCs
• Ventana CEO to Deliver a Keynote at RISC-V Summit Europe
• True Circuits Introduces the JSPICE™ Design Environment (JDE™) at the Design Automation Conference
• Figuring Out the Carbon Footprint of an Individual Chip
• RISC-V in Space Workshop in Gothenburg on April 2-3, 2025!

Thursday, June 20, 2024

• Tenstorrent Licenses Baya Systems' Fabric into next-generation AI and Compute Chiplet Solutions
• Baya Systems Introduces New Technology to Transform SoCs and Chiplets for Emerging Applications
• Andes Technology Showcases Leadership in AI and Automotive Applications at RISC-V Summit Europe 2024

Wednesday, June 19, 2024

• Dovetail Electric Aviation adopts Siemens Xcelerator to pioneer sustainable aviation
• Alphawave Semi Unlocks 1.2 TBps Connectivity for High-Performance Compute and AI Infrastructure with 9.2 Gbps HBM3E Subsystem
• lowRISC and Microsoft Collaborate to Help Bring the Revolutionary CHERIoT-Ibex Core to Production Grade
• Primemas Selects Achronix Embedded FPGA Technology For System-on-Chip (SoC) Hub Chiplet Platform
• System-level UCIe IP for early architecture analysis of 3D Chiplet Design and Packaging
• PQShield raises $37m in Series B funding to deliver the widespread commercial adoption of quantum resistant cryptography
• Breker Verification Systems Readies RISC-V CoreAssurance and SoCReady SystemVIP for Automated, Certification-level RISC-V Verification Coverage

Wednesday, June 19, 2024

• Movellus Introduces Aeonic Powerâ„¢ Product Family for On-Die Voltage Regulation

Tuesday, June 18, 2024

• onsemi selects Czech Republic for SiC production for advanced power semiconductors
• Slide Shows Samsung May be Developing a RISC-V CPU for In-memory AI Chip
• Intel 3 '3nm-class' process technology is in high-volume production
• Rapidus Set to Open 2-nm Pilot Fab, CEO Says
• EU proposes budget cuts to tech programmes in 2025
• Why do defects occur in battery production? Explainable AI supports process optimization.
• Global partnership unveils quantum-safe hardware root-of-trust for cellular IoT
• Alphawave Reveals Multiprotocol I/O Chiplet Tapeout, Collabs with Arm, Samsung
• YorChip announces Low Latency 200G Chiplet for edge AI
• M31 Announces the Launch of Advanced LPDDR Memory IP to Support HPC Applications
• Dream Chip and Cadence Demo Automotive SoC Featuring Tensilica AI IP at embedded world 2024
• Movellus Introduces Aeonic Power™ Product Family for On-Die Voltage Regulation
• OPENEDGES to Premiere PHY Vision 2.0 at Design Automation Conference 2024

Monday, June 17, 2024

• Are We Prepared for Cyberthreats in The New Era of Transportation?
• Samsung Foundry Struggles with Yield and Power Efficiency Issues
• Intel 3 Represents an Intel Foundry Milestone
• QuickLogic Joins Intel Foundry Accelerator IP and USMAG Alliance Programs
• Faraday to Exhibit Next-gen ASIC Solutions at DAC 2024
• Sequans Announces a New $15 Million Licensing Agreement