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Thursday, April 18, 2024

• Fraunhofer IIS Opens Laboratory in Space
• Brisbane Silicon publishes DPTx 1.4 IP Core
• TSMC Reports First Quarter EPS of NT$8.70
• Omni Design Technologies Joins Intel Foundry Accelerator IP Alliance
• Efabless Announces the Release of the OpenLane 2 Development Platform, Transforming Custom Silicon Design Flows
• DVB-S2X Wideband LDPC/ BCH Decoder IP Core Available For Integration From Global IP Core
• GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers

Wednesday, April 17, 2024

• Cadence Collaborates with MemVerge to Increase Resiliency and Cost-Optimization of Long-Running High-Memory EDA Jobs on AWS Spot Instances
• M31 Successfully Validates 5nm IP Solution to Empower Global AI Applications
• Dolphin Design expands GoAsic partnership to enhance the semiconductor Industry's Supply Chain
• Cadence Unveils Palladium Z3 and Protium X3 Systems to Usher in a New Era of Accelerated Verification, Software Development and Digital Twins
• Cadence Announces Most Comprehensive True Hybrid Cloud Solution to Provide Seamless Data Access and Management
• Demonstration of Weebit ReRAM on GF 22FDX® Wafers at EW24
• Faraday Partners with Arm to Innovate AI-driven Vehicle ASICs

Tuesday, April 16, 2024

• Infineon provides FOXESS with power semiconductors to improve efficiency and power density of energy storage applications
• STMicroelectronics opens up the FD-SOI era for MCU
• Samsung Develops Industry's Fastest 10.7Gbps LPDDR5X DRAM, Optimized for AI Applications
• Cadence Unveils Palladium Z3 and Protium X3 Systems to Usher in a New Era of Accelerated Verification, Software Development and Digital Twins
• JEDEC Updates JESD79-5C DDR5 SDRAM Standard: Elevating Performance and Security for Next-Gen Technologies
• Alphawave Semi: FY 2023 and 2024 YTD Trading Update and Notice of Results
• Zhuhai Chuangfeixin: OTP IP Based on 90nm CMOS Image Sensor Process Technology Successfully Mass-Produced
• Silvaco Announces Expanded Partnership with Micron Technology
• U.S. Subsidy for TSMC Has AI Chips, Tech Leadership in Sight
• Rivos Raises More Than $250M Targeting Data Analytics and Generative AI Markets

Monday, April 15, 2024

• Emotors adopts Siemens' Simcenter solutions for NVH testing of next-generation automotive e-drives
• TSMC Reports Solid Earnings Boost Amid Surging AI Demand
• STMicroelectronics Publishes 2024 Sustainability Report
• Challenges in designing automotive radar systems
• Arm accelerates Edge AI with Ethos-U NPU and IoT reference design platform
• ITRI launches AIoT certification center with Arm
• IP block covers Wi-Fi 6, Bluetooth 5.4 dual mode and IEEE 802.15.4 for IoT chips
• Movellus Extends Droop Management Leadership with Aeonic Generateâ„¢ AWM3
• Fraunhofer IIS offers JPEG XS plugin for NVIDIA´s Holoscan for Media Architecture
• CMC Microsystems and AIoT Canada Sign Memorandum of Understanding to support IoT and semiconductor ecosystem growth in Canada
• Movellus Extends Droop Management Leadership with Aeonic Generate™ AWM3
• Fraunhofer IIS offers JPEG XS plugin for NVIDIAs Holoscan for Media Architecture
• OPENEDGES Unveils ENLIGHT Pro: A High-Performance NPU IP Quadrupling its Previous Generation's Performance

Sunday, April 14, 2024

• U.S. Subsidy for TSMC Has AI Chips, Tech Leadership in Sight
• Samsung gets $6.4bn Chips Act money
• Rapidus opens sales office in Silicon Valley
• A Brief and Personal History of EDA, Cadence, Synopsys, and Mentor Graphics - The EDA Era
• Ceva Wireless Platform IP Family Accelerates Enhanced Connectivity in MCUs and SOCs
• Siemens and Microsoft to converge Digital Twin Definition Language with W3C Thing Description Standard
• Semiconductor Capacity Is Up, But Mind the Talent Gap
• New Wave Design and Verification Announces Strategic Brand Evolution to Sharpen Focus on Innovation and Growth
• Microchip Technology Acquires Neuronix AI Labs
• Khronos Releases OpenXR 1.1 to Further Streamline Cross-Platform XR Development
• intoPIX Unveils Titanium at NAB for Accelerating IP Media Workflows
• Brazil and Europe sign innovative project with RISC-V technology for HPC
• Unveiling Silicon-proven USB 3.0 PHY IP Core in 22nm, Elevating High-Speed Data Transmission with Advanced Transceiver Technology, backward compatible with USB 2.0

Friday, April 12, 2024

• VISC: The New Coprocessing RISC-V Architecture for AI Efficiency

Thursday, April 11, 2024

• Kudelski IoT's Semiconductor Alliances set to redefine IoT provisioning
• Logic Fruit Technologies Inc. Excitedly Welcomes Mr. Akshaya Sharma as the new CEO of US Operations
• Creonic GmbH Introduces Fast Fourier Transform IP Core
• intoPIX Unveils Latest JPEG XS FPGA Cores with Nextera-Adeas ST2110/IPMX, Streamlining IPMX Development at NAB Show

Wednesday, April 10, 2024

• Think Silicon and Edge Impulse Democratize ML on NEOX® for Wearables and AIoT
• Think Silicon and Edge Impulse Democratize ML on NEOX® for Wearables and AIoT
• Xiphera and Kaviaz Technology Announce a Partnership for IP Distribution in Taiwan

Tuesday, April 9, 2024

• Winners of the Embedded World awards
• Innova finalizes its flow and resource management software platform and opens up to the international market
• TSMC Arizona and U.S. Department of Commerce Announce up to US$6.6 Billion in Proposed CHIPS Act Direct Funding, the Company Plans Third Leading-Edge Fab in Phoenix
• Tiempo Secure - CryptoNext Security partnership, bringing High-End Post-Quantic IP Security innovation to the next level.
• Google Cloud Delivers Customized Silicon Powered by Arm Neoverse for General-Purpose Compute and AI Inference Workloads
• TSMC March 2024 Revenue Report

Monday, April 8, 2024

• Xiphera Launches nQruxâ„¢ Family of Hardware Trust Engines for Hardware-Isolated Cryptographic Services and Computing Environments
• Semiconductor design innovation: how EDA initiates the digitalization journey for a smarter, sustainable future.
• Intel Unleashes Enterprise AI with Gaudi 3, AI Open Systems Strategy and New Customer Wins
• Synopsys Launches New Offering for Comprehensive Software Supply Chain Security
• RISC-V compiler toolset targets automotive functional safety
• AI-Driven HBM Uptake Is Power-Sensitive
• MIPS Continues To Expand With The Addition Of Industry Leaders from NVIDIA, Google and SiFive
• Rebellions Selects Arteris for Its Next-Generation Neural Processing Unit Aimed at Generative AI
• Electronic System Design Industry Posts $4.4 Billion in Revenue in Q4 2023, ESD Alliance Reports
• Xiphera Launches nQrux™ Family of Hardware Trust Engines for Hardware-Isolated Cryptographic Services and Computing Environments
• Autotalks and Secure-IC Collaborate to Create the Most Secure V2X Communication Chipset
• Xiphera Launches nQrux™ Family of Hardware Trust Engines for Hardware-Isolated Cryptographic Services and Computing Environments
• TASKING presents compiler toolset for RISC-V in safety- and security-critical automotive applications
• SiFive Unveils the HiFive Premier P550, the First Commercially Available Out-of-Order RISC-V Development Board
• Ambiq and PUFsecurity Join Forces on Energy-Efficient, Security-Enhanced SoC with PUF-based Root of Trust
• Arm Accelerates Edge AI with Latest Generation Ethos-U NPU and New IoT Reference Design Platform
• VeriSilicon showcased its latest power-efficient IP applications at Embedded World 2024