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Sunday, March 10, 2024

• Former Moortec executives create chip monitor startup
• Free configurator puts the power of full core customisation into hands of customers
• Elevate the performance of your Automotive Application by integrating the IP cores of a 14-bit wideband Time-Interleaved Pipeline Data Converters
• Omni Design Technologies Offers Swift™ Data Converters for Advanced Software Defined Radio (SDR) Solutions
• Alphawave Semi Demonstrates 3nm Silicon-Proven 24Gbps Universal Chiplet Express (UCIe) Subsystem for High-Performance AI Infrastructure
• Re-imagining Imagination Technologies
• OPENEDGES and SEMIFIVE Partnership Reinforce the SoC Platform

Thursday, March 7, 2024

• TSMC February 2024 Revenue Report
• M31's Revenue Grew Against the Trend by 18.5% Last Year and Will Increase Investment in Advanced Processes This Year
• Credo Launches 112G PAM4 SerDes IP for TSMC N3 Process Technology
• CAST Adds I3C Secondary Controller Core to MIPI IP Product Line

Wednesday, March 6, 2024

• Samsung to use recycled neon gas in chip manufacturing
• nepes corporation expands IC packaging capabilities for the 3D-IC era with advanced design flows from Siemens
• Marvell Announces Industry's First 2nm Platform for Accelerated Infrastructure Silicon
• sureCore announces ultra-low power memory IP for AI applications
• SignatureIP announces PCIe Gen 6 Controller IP

Tuesday, March 5, 2024

• QuickLogic (QUIK) Secures Five-year Contract for Its eFPGA IP
• Revolutionizing Fuel Cell Production: Fraunhofer IPA and Partners Launch H2FastCell Robotics
• Synopsys Supports AI-Bogged Data Centers With First 1.6T Ethernet IP
• BrainChip Adds Edge Box to Chip and IP Offerings
• Niobium and Veriest collaborate to develop the world's fastest complete FHE accelerator chip
• Cadence to Acquire BETA CAE, Expanding into Structural Analysis
• GUC Monthly Sales Report - February 2024
• Industry Leading PPA DSP Available For All Existing EFLX eFPGA
• Flex Logix Joins Intel Foundry USMAG Alliance
• Ethernovia Unveils World's First Single and Quad Port, 10G to 1G Automotive PHY in 7nm
• JEDEC Publishes GDDR7 Graphics Memory Standard
• Imsys develops RISC-V core, looks to AI in space
• Nuclei System Technology collaborates with Siemens to deliver RISC-V Processor Trace Encoder solution
• Taalas emerges from stealth with $50 million in funding and a groundbreaking silicon AI technology
• UMC Reports Sales for February 2024

Monday, March 4, 2024

• The promise of OTS-only memories for next-gen compute
• QuickLogic Announces eFPGA IP Contract for TSMC N12e™ Process Technology
• Semidynamics puts the power of full core customisation into hands of customers
• Scalable Extreme-Speed IPsec Added to Xiphera's Security Protocols Portfolio
• BrainChip Boosts Space Heritage with Launch of Akida into Low Earth Orbit

Monday, March 4, 2024

• Rambus Initiates Accelerated Share Repurchase Program

Sunday, March 3, 2024

• Credo to Present at 36th Annual Roth Conference
• Siemens Unveils EcoTech Label for Enhanced Product Sustainability Transparency
• French cloud Scaleway starts renting Alibaba's RISC-V SoC
• Scaleway launches its RISC-V servers in the cloud, a world first and a firm commitment to technological independence
• Accellera Approves Verilog-AMS 2023 Standard for Release
• Agnisys to Showcase Expertise at DVCon US with Exclusive Short Workshop and Tutorial Sessions
• VeriSilicon's industry-leading embedded GPU IP powers HPMicro's high-performance HPM6800 series RISC-V MCU
• Intel Launches Altera, Its New Standalone FPGA Company
• Unleash Next-Gen Speeds with Silicon-Proven USB 3.0 PHY IP Cores with Type-C Support in Multiple Process Nodes
• Interview: Mahesh Tirupattur, executive VP of Analog Bits - "Be Passionate, Fail Fast and Recover Quick"
• Agile Analog's Christelle Faucon: "Diversity and Equality Are Critical"

Thursday, February 29, 2024

• Rambus Initiates Accelerated Share Repurchase Program
• European Union Seeks Chip Sovereignty Using RISC-V
• Partners Applaud Intel Foundry's Wider Ecosystem Approach
• ADTechnology and CoSignOn/CoreLink Sign MOU to Further Collaborate on High-Bandwidth Memory for Next-Generation HPC
• Sondrel announces two new design contract wins plus two existing Design Consultancy contracts extended

Wednesday, February 28, 2024

• Synopsys Launches Industry's First Complete 1.6T Ethernet IP Solution to Meet High Bandwidth Needs of AI and Hyperscale Data Center Chips
• VeriSilicon NPU IP is shipped in over 100 million AI-enabled chips worldwide
• Cadence Expands Tensilica Vision Family with Radar Accelerator and New DSPs Optimized for Automotive Applications
• proteanTecs Joins Arm Total Design, Brings Lifecycle Health and Performance Monitoring to Arm-based Custom SoCs

Tuesday, February 27, 2024

• Alliance aims to drive AI into the radio network
• FPT Corporation and Siemens Forge Partnership to Revolutionize Manufacturing and Digital Transformation
• AI for saving lives in automotive
• Cadence Expands Tensilica Vision Family with Radar Accelerator and New DSPs Optimized for Automotive Applications
• Alliance to drive AI into the radio network
• Intel puts 1nm process (10A) on the roadmap for 2027 - also plans for fully AI-automated factories with 'Cobots'
• Ceva Joins Arm Total Design to Accelerate Development of End-to-End 5G SoCs for Infrastructure and NTN Satellites
• QuickLogic Signs 7-Figure eFPGA IP Contract for GlobalFoundries' 12LP Process
• RAAAMâ„¢ Memory Technologies Expands Leadership Team With the Addition of Eli Leizerovitz as Chief Business Officer
• Cornell Tech Joins BrainChip University AI Accelerator Program

Tuesday, February 27, 2024

• Microchip's Low-Cost PolarFire® SoC Discovery Kit Makes RISC-V and FPGA Design More Accessible for a Wider Range of Embedded Engineers