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Monday, January 29, 2024

• Intel Plans to Utilize TSMC's 2nm Technology in Its New Nova Lake Processor
• Device and Data Security in the Embedded Systems
• Alphawave Semi and proteanTecs Collaborate to Provide System Insights and Analytics for Custom Silicon and Chiplets
• Arteris Selected by Rain AI for Use in the Next Generation of AI
• DCD celebrates 25 years

Sunday, January 28, 2024

• Strengthening the security of broadband 5G/6G communication networks
• TASKING Supports Arm Architecture for Automotive Development
• Silvaco Joins GaN Valley™, a Wide Bandgap Semiconductor Innovation Ecosystem in Europe
• INTERCHIP achieves 3x faster verification for next-gen clocking oscillator with Siemens' advanced analog and mixed-signal EDA technology
• T2M-IP Unveils Best-Selling DVB-T2/T Demodulator IP Core with Cutting-Edge Features, Silicon Proven and Ready to License

Thursday, January 25, 2024

• Siemens-Heineken Partnership & Digital Twin Decarbonisation
• Beyond Silicon: New Sustainable Method for Creating Organic Semiconductors
• CEO Interview: Charlie Janac of Arteris -- "Pick a Viable Path, Don't Give Up"
• AMIQ EDA Releases Major Customer-Focused Product Line Update

Wednesday, January 24, 2024

• Intel and UMC Announce New Foundry Collaboration
• Logic Fruit Technologies Launches FlexRay RTL IP CORE
• China ten years behind and staying there
• Qualinx partners with EU Space Agency to develop a GNSS receiver for a service to detect spoofing and boost resilience
• Xylon's logicBRICKS HDR ISP IP Suite Gets an RGB-IR Image Processing Upgrade
• Frontgrade Gaisler and RISC-V's Space Journey
• Solving the decarbonization equation
• eMemory's Security-Enhanced OTP Qualifies on TSMC N4P Process, Pushing Forward in High-Performance Leading Technology

Wednesday, January 24, 2024

• Keysight Introduces Chiplet PHY Designer for Simulating D2D to D2D PHY IP Supporting the UCIeâ„¢ Standard

Tuesday, January 23, 2024

• SoC design: When a network-on-chip meets cache coherency
• Report: Apple will be first to receive TSMC's 2nm chips starting in 2025
• Keysight Introduces Chiplet PHY Designer for Simulating D2D to D2D PHY IP Supporting the UCIe™ Standard

Monday, January 22, 2024

• Marquee Semiconductor Engages Industry Veteran Gideon Intrater as Strategic Advisor
• Canada Feeling Out Its Role in Global Chip Supply Chain
• Thales and Quantinuum Launch Starter Kit to help Enterprises prepare for Post-Quantum Cryptography Changes Ahead
• Get Rolling: Automotive AI and ADAS Innovations
• EU Commission readies establishment of AI Office
• Siemens brings thermal digital twin technology to the electronics supply chain
• Phison Deploys Cadence Cerebrus AI-Driven Chip Optimization to Accelerate Product Development
• Strengthening the security of broadband 5G/6G communication networks
• Sondrel completes a multi-billion transistor chip design at 5nm
• Revolutionizing ProAV Networks: intoPIX Unveils TicoXS FIP for Unmatched 4K & 8K AVoIP Excellence at ISE 2024
• Infineon and GlobalFoundries extend long-term agreement with focus on automotive microcontrollers
• Menta exhibits at Chiplet Summit and presents its new scalable chiplet platform, MOSAICS-LP

Monday, January 22, 2024

• Renesas Extends Tender Offer for Proposed Acquisition of Sequans

Sunday, January 21, 2024

• Alphawave Semi - Q4 2023 Trading and Business Update
• T2M Unveils ASIL B-Certified CAN and LIN IP Cores, Securing 11 Licenses in 2023

Saturday, January 20, 2024

• Samsung's 2nd-Gen 3nm Process, SF3, Has Begun Trial Production

Thursday, January 18, 2024

• AI to drive strong chip market growth in 2024, says TSMC
• TSMC Reports Fourth Quarter EPS of NT$9.21
• Cadence Unveils New Palladium Z2 Apps with Industry's First 4-State Emulation and Mixed-Signal Modeling to Accelerate SoC Verification

Wednesday, January 17, 2024

• Frontgrade Gaisler and RISC-V's Space Journey
• ITRI and TSMC Collaborate on Advancing High-Speed Computing with SOT-MRAM
• Samsung and TSMC competing to dominate 2nd-gen 3nm at global foundry industry