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Wednesday, July 19, 2023

• Schneider takes lead to decarbonise semiconductor value chain
• SK hynix adopts Siemens' Polarion to help gain Korea's first ASPICE certification
• Arm expands open-source partnerships to reinforce commitment to open collaboration
• Synopsys Accelerates Advanced Chip Design with First-Pass Silicon Success of IP Portfolio on TSMC 3nm Process
• Semidynamics announces fully customisable, 4-way, Atrevido 423 RISC-V core for big data applications
• Thalia Secures $2.7 Million Funding to Strengthen Position as Leading IP Reuse Partner for Semiconductor Industry
• BrainChip's Latest US Patent Award Extends Intellectual Property Strength and its Leadership in Edge Learning

Tuesday, July 18, 2023

• Minimize Design Risk and Achieve First-Pass Silicon Success on TSMC's N3E Process
• HCL Technologies US$ 300 Million Bet on India's Semiconductor Industry
• VSORA Announces All-in-One Single Chip Architecture to Meet Generative AI Processing Challenges
• How China is Building an Open National Chip Plan Around RISC-V
• Schneider Electric Partners with Intel and Applied Materials to Decarbonize Semiconductor Value Chain
• How semiconductor firms are chipping in on sustainability
• Passport for a sustainable European electronics supply chain
• VSORA reveals Jotunn generative AI processor
• Cadence, GlobalFoundries, Hoerzentrum Oldenburg and Leibniz University Hannover Collaborate to Advance Hearing Aid Technology
• Lightelligence Partners With ZeroPoint Technologies to Increase Data Center Connectivity Performance by Up to 50%
• Expedera Announces LittleNPU AI Processors for Always-Sensing Camera Applications
• New Wave Design and Verification Appoints Ike Song to Advisory Committee

Monday, July 17, 2023

• Samsung Shipping First GAAFET Silicon; 3nm and 4nm Yields Are Improving - Report
• OmniSpeech, Cadence Tensilica team up on voice AI technology
• Startups Help RISC-V Reshape Computer Architecture
• DENSO Adopts Attopsemi's OTP to Upgrade Future Automotive Products

Sunday, July 16, 2023

• Radiofrequency & silicon photonics for high-performance, low-power, secure data transmission
• DAC 2023: RISC-V is not in the future, it's now
• Cadence Joules RTL Design Studio delivers breakthrough gains
• SMIC: Resignation of Chairman of the Board and Executive Director Appointment of Chairman of the Board and Change of Authorised Representative
• Allegro DVT joins the DVB Project
• Cadence Unveils Joules RTL Design Studio, Delivering Breakthrough Gains in RTL Productivity and Quality of Results
• The industry's first RISC-V IoT security chip, "Towngas Chip", had sold over 1,000,000 pieces
• GMAC Intelligence Goes Big with BrainChip Partnership
• RED Semiconductor and Crypto Quantique agree MOU for Development of Chip with Advanced Processing Capability and Quantum-based Security
• Accelerate the verification process of your design IP by licensing the Verification IP Cores, which come equipped with a solid track record of automotive compatibility

Thursday, July 13, 2023

• M31 Partners with Intel IFS Alliance to Present Latest IP Development Achievements

Wednesday, July 12, 2023

• Rambus Delivers Quantum Safe IP Solutions with Next-Generation Root of Trust for Data Center Security
• Global Semiconductor Equipment Sales Forecast: $87 Billion in 2023 With 2024 Rebound, SEMI Reports
• Truechip Announces First Customer Shipment Of USB4v2 Verification IP
• European Commission Approves Broadcom's Acquisition of VMware
• The Future of Mobility: Fraunhofer IPMS drives the Revolution in Vehicle Architecture

Tuesday, July 11, 2023

• Intelligent terminals applications given an innovation enhancement through AI acceleration
• Cadence Digital, Custom/Analog Design Flows Certified and Design IP Available for Intel 16 FinFET Process
• T2M Presents Silicon Proven MIPI D-PHY and DSI Controller IP Cores in 12FFC & 22ULL For Your Next Generation Display Products
• Crypto Quantique Selected for European Innovation Council (EIC) Grant Funding
• Cycuity Achieves ISO/SAE 21434 Certification for Automotive Cybersecurity Compliance

Monday, July 10, 2023

• Arasan's MIPI CSI-2 IP achieves ISO26262 ASIL-C Certification for MIPI C-PHY Connectivity
• Faraday's Launched SerDes Advanced Service to Accelerate ASICs into Production
• Spectral Design & Test Inc joins TSMC OIP IP Alliance
• Synopsys Delivers Certified EDA Flows and High-Quality IP for Intel 16 Process
• Siemens' Calibre platform now certified for IFS' Intel 16 process technology
• 'Correct by construction' tool for chip power layout down to 2nm
• Imperas details verification of automotive AI RISC-V vector processor IP
• Second contest for Generative AI chip design
• proteanTecs and Teradyne Partner to Bring Machine Learning-driven Telemetry to SoC Testing
• TSMC to construct second chip plant in Japan, aims to start production in 2026

Sunday, July 9, 2023

• TSMC June 2023 Revenue Report
• Siemens expand collaboration with AWS to help IC and electronics design customers accelerate innovation
• Siemens advances intelligent custom IC verification platform with new, AI-powered Solido Design Environment
• Electronic System Design Industry Logs $4 Billion in Revenue in Q1 2023, ESD Alliance Reports
• Cadence and Imperas Support NSITEXE in the Development of Advanced RISC V Vector Processor IP for Automotive AI Applications
• Siemens unveils Calibre DesignEnhancer for Calibre correct-by-construction IC layout optimization
• Alphawave Semi Spearheads Chiplet-Based Custom Silicon for Generative AI and Data Center Workloads with Successful 3nm Tapeouts of HBM3 and UCIe IP
• Xpeedic Launches High-Speed Digital Signal Integrity, Power Integrity Suite at Design Automation Conference
• End-to-end design and verification for PCIe 6.0
• Siemens advances intelligent custom IC verification platform with new, AI-powered Solido Design Environment
• Samsung Reports Net Zero Progress, Pledges Over $5B by 2030
• Bespoke EDA Differentiates Silicon Chips
• T2M invites Customers to explore High Performance, Cost-effective and Innovative IP Cores Solutions at DAC 2023