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Thursday, April 27, 2023

• State aid: Commission approves French measure to support STMicroelectronics and GlobalFoundries to set up new microchips plant
• Alphawave Semi: Q1 2023 Trading and Business Update
• Alphawave to suspend shares

Thursday, April 27, 2023

• Cadence Delivers New Design Flows Based on the Integrity 3D-IC Platform in Support of TSMC 3Dbloxâ„¢ Standard

Wednesday, April 26, 2023

• STMicroelectronics Publishes 2023 Sustainability Report
• TSMC on track to roll out advanced 2nm chips by 2025
• Siemens announces certifications for TSMC's latest processes, celebrates recent achievements for Siemens and TSMC collaboration
• Lattice Extends Low Power FPGA Portfolio with Launch of MachXO5T-NX Advanced System Control FPGAs
• Xiphera adds lightweight cryptography to its stream cipher portfolio
• M31 demonstrates high-speed interface IP development achievements on TSMC's 7nm & 5nm process technologies
• Cadence Digital and Custom/Analog Design Flows Certified for TSMC's Latest N3E and N2 Process Technologies
• Revenue Decline of Global Top 10 IC Design Houses Expanded to Nearly 10% in 4Q22, Decline Expected to Continue into 1Q23, Says TrendForce
• Cadence Delivers New Design Flows Based on the Integrity 3D-IC Platform in Support of TSMC 3Dblox™ Standard
• Weebit Nano ReRAM now commercially available; fab & customer agreements progressing
• Esperanto Technologies Launches New Cloud Access Program to Broaden Access to its Massively Parallel, Low Power RISC-V Solutions
• HDL Design House develops its first full SoC from architecture definition to tapeout for an external customer
• Creonic Introduces FEC IP Core Solution for SDA Free-Space Optical OCT V3.0 Standard
• TSMC Showcases New Technology Developments at 2023 Technology Symposium
• Signature IP Corporation Demonstrates Configurable NoC Products at Design & Reuse IP SoC Day

Tuesday, April 25, 2023

• CEA-Leti: a Top 5 global leader of semiconductor patents
• High-precision microsensor technology for a wide application range
• Xiphera joins Microchip Technology's FPGA Design Partner program
• Cadence Delivers New Design Flows Based on the Integrity 3D-IC Platform in Support of TSMC 3Dblox™ Standard
• Cadence Collaborates with GUC on AI, HPC and Networking in Advanced Packaging Technologies
• Alphawave Semi Showcases 3nm Connectivity Solutions and Chiplet-Enabled Platforms for High Performance Data Center Applications
• Synopsys, Ansys and Keysight Collaborate with TSMC to Boost Performance of Autonomous Systems with New mmWave Reference Flow
• Weebit Nano successfully secures US$40 million to accelerate development and commercial roll-out of its ReRAM
• Fraunhofer IIS/EAS Selects Achronix Embedded FPGAs (eFPGAs) to Build Heterogeneous Chiplet Demonstrator
• Arteris IP Licensed by Axelera AI to Accelerate Computer Vision at the Edge

Monday, April 24, 2023

• Infrared vision: exceptionally sharp images
• UK government announces £100m investment in AI foundation models
• 6G is Happening, and Here's What You Need to Know
• Cadence and TSMC Collaborate on N16 79GHz mmWave Design Reference Flow to Accelerate Radar, 5G and Wireless Innovation
• Cadence Custom Design Migration Flow Accelerates Adoption of TSMC N3E and N2 Process Technologies
• Synopsys and TSMC Collaborate to Jumpstart Designs on TSMC's N2 Process with Optimized EDA Flows
• Sondrel engages The SHD Group to assist in bringing Architecting the Future to the American market
• Synopsys and TSMC Collaborate to Jumpstart Designs on TSMC's N2 Process with Optimized EDA Flows
• Rapid Silicon Launches Vega eFPGA IP for Programmable Solutions
• Attopsemi's Revolutionary I-fuse® OTP Silicon-Proven on FinFET Technology
• Agile Analog launches innovative digitally wrapped analog IP subsystems
• Cadence Accelerates Hyperscale SoC Design with Next-Generation 112G Extended Long-Reach SerDes IP on TSMC's N4P Process
• Analog Bits to Demonstrate Working Silicon on TSMC N3E Process at TSMC 2023 North America Technology Symposium
• Cadence Tapes Out 16G UCIe Advanced Package IP on TSMC's N3E Process Technology
• Andes Technology's N25F RISC-V Processor Enables Superior Performance And Low Power For Phison's X1 Enterprise SSD Controller
• OPENEDGES' 12nm LPDDR5/4 Memory Subsystem IP that Drives Innovation Licensed by ASICLAND
• Attopsemi's Revolutionary I-fuse® OTP Silicon-Proven on FinFET Technology

Sunday, April 23, 2023

• Design IP revenues grew 20% last year
• Arm prototype processor raises business model questions
• Arm reportedly developing 'advanced' test chip for customers
• Flex Logix Announces InferXâ„¢ High Performance IP for DSP and AI Inference
• VyperCore Announces £4 million in Seed Funding
• Synopsys, TSMC and Ansys Strengthen Ecosystem Collaboration to Advance Multi-Die Systems
• Flex Logix Announces InferX™ High Performance IP for DSP and AI Inference
• Arm reported to be building a chip
• Dilithium core complements Xiphera's xQlave® family of post-quantum cryptography
• Introducing High-Speed Fractional PLL IP Cores with SSC that offers exceptional features in different process technologies
• Weebit Nano raises $15 million via upsized and scaled-back SPP
• Coherent Logix collaborates with Omni Design, AkiraNET Co. and Socionext to deliver reference design for Wi-Fi 6E/7

Saturday, April 22, 2023

• Omni Design's High Performance Analog Front Ends are Adopted in Socionext's Next Generation Communications SoCs
• Marvell Demonstrates Industry's First 3nm Data Infrastructure Silicon

Wednesday, April 19, 2023

• Anchoring Trust to Enhance IoT Security
• EdgeQ Closes $75M Series-B Investment and Ramps to Customers' Demand for Its Award-Winning 5G+AI Base Station-on-a-Chip for 5G Networks
• GlobalFoundries Files Lawsuit Against IBM to Protect its Intellectual Property and Trade Secrets
• TSMC Reports First Quarter EPS of NT$7.98
• EU agrees Chips Act terms
• EdgeCortix Expands Delivery of its Industry Leading SAKURA-I AI Co-processor Devices and MERA Software Suite
• Rambus Accelerates AI Performance with Industry-Leading 24 Gb/s GDDR6 PHY
• The Six Semiconductor of OPENEDGES Receives Best International Business Award from ACCE

Tuesday, April 18, 2023

• The Environmental Impact Of Using Plastic To Make Microchips
• The Need for Security is Everywhere. Intrinsic ID Showcases Expertise and PUF Innovations at Key Industry Events
• Volkswagen wants to become more agile with new R&D centre in China
• Cadence Unleashes the Future of Analog, Custom and RFIC Design with Pioneering AI-Powered Virtuoso Studio
• Rambus Accelerates AI Performance with Industry-Leading 24 Gb/s GDDR6 PHY
• Esperanto Technologies Announces RISC-V Industry Milestone of Generative AI Models Running on ET-SoC-1; Access to be Made Available to the RISC-V Research Community
• Europe consolidates quantum production and test
• Silicon Interfaces enhances Functional Safety ISO 26262-Compliant ASIL C Services Solution for Automotive
• The Need for Security is Everywhere. Intrinsic ID Showcases Expertise and PUF Innovations at Key Industry Events

Monday, April 17, 2023

• Arm liable for $8.5B SoftBank loan if IPO is a no-show
• Nordic Reveals "Revolution" of Wireless SoC Line: The nRF54 Series
• Mixel MIPI C-PHY/D-PHY Combo IP Integrated into Hercules Microelectronics HME-H3 FPGA
• Rapid Silicon Partners with Elastics.cloud on CXL 3.0 Dual Mode Controller IP to Enhance its Custom FPGA Solutions
• eMemory's Security-enhanced OTP Qualifies on TSMC N5 Process and Continues to Tackle Automotive Solutions
• Cadence Demonstrates Interoperability with SK hynix's Highest Speed LPDDR5T Mobile DRAM at 9600Mbps

Sunday, April 16, 2023

• Spanish startup performs RISC-V open core surgery
• Process agnostic fully customisable RISC-V IP cores
• Cadence extends TSMC deal for physical verification on Azure
• Cadence Extends Collaboration with TSMC and Microsoft to Advance Giga-Scale Physical Verification in the Cloud
• TSMC could partner with Bosch for 28nm fab in Germany
• Introducing the Cutting-Edge USB 3.0/ PCIe 3.0 Combo PHY IP Core in 28HPC+ for High-Performance SoC Designs
• Arm could be on the hook for $8.5bn of Softbank debt
• DVB-S2X LDPC/ BCH Encoder and Decoder IP Core Available For Integration From Global IP Core
• Semidynamics launches world's first fully customisable RISC-V IP cores