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Thursday, January 25, 2024

• Siemens-Heineken Partnership & Digital Twin Decarbonisation
• Beyond Silicon: New Sustainable Method for Creating Organic Semiconductors
• CEO Interview: Charlie Janac of Arteris -- "Pick a Viable Path, Don't Give Up"
• AMIQ EDA Releases Major Customer-Focused Product Line Update

Wednesday, January 24, 2024

• Intel and UMC Announce New Foundry Collaboration
• Logic Fruit Technologies Launches FlexRay RTL IP CORE
• China ten years behind and staying there
• Qualinx partners with EU Space Agency to develop a GNSS receiver for a service to detect spoofing and boost resilience
• Xylon's logicBRICKS HDR ISP IP Suite Gets an RGB-IR Image Processing Upgrade
• Frontgrade Gaisler and RISC-V's Space Journey
• Solving the decarbonization equation
• eMemory's Security-Enhanced OTP Qualifies on TSMC N4P Process, Pushing Forward in High-Performance Leading Technology

Wednesday, January 24, 2024

• Keysight Introduces Chiplet PHY Designer for Simulating D2D to D2D PHY IP Supporting the UCIeâ„¢ Standard

Tuesday, January 23, 2024

• SoC design: When a network-on-chip meets cache coherency
• Report: Apple will be first to receive TSMC's 2nm chips starting in 2025
• Keysight Introduces Chiplet PHY Designer for Simulating D2D to D2D PHY IP Supporting the UCIe™ Standard

Monday, January 22, 2024

• Marquee Semiconductor Engages Industry Veteran Gideon Intrater as Strategic Advisor
• Canada Feeling Out Its Role in Global Chip Supply Chain
• Thales and Quantinuum Launch Starter Kit to help Enterprises prepare for Post-Quantum Cryptography Changes Ahead
• Get Rolling: Automotive AI and ADAS Innovations
• EU Commission readies establishment of AI Office
• Siemens brings thermal digital twin technology to the electronics supply chain
• Phison Deploys Cadence Cerebrus AI-Driven Chip Optimization to Accelerate Product Development
• Strengthening the security of broadband 5G/6G communication networks
• Sondrel completes a multi-billion transistor chip design at 5nm
• Revolutionizing ProAV Networks: intoPIX Unveils TicoXS FIP for Unmatched 4K & 8K AVoIP Excellence at ISE 2024
• Infineon and GlobalFoundries extend long-term agreement with focus on automotive microcontrollers
• Menta exhibits at Chiplet Summit and presents its new scalable chiplet platform, MOSAICS-LP

Monday, January 22, 2024

• Renesas Extends Tender Offer for Proposed Acquisition of Sequans

Sunday, January 21, 2024

• Alphawave Semi - Q4 2023 Trading and Business Update
• T2M Unveils ASIL B-Certified CAN and LIN IP Cores, Securing 11 Licenses in 2023

Saturday, January 20, 2024

• Samsung's 2nd-Gen 3nm Process, SF3, Has Begun Trial Production

Thursday, January 18, 2024

• AI to drive strong chip market growth in 2024, says TSMC
• TSMC Reports Fourth Quarter EPS of NT$9.21
• Cadence Unveils New Palladium Z2 Apps with Industry's First 4-State Emulation and Mixed-Signal Modeling to Accelerate SoC Verification

Wednesday, January 17, 2024

• Frontgrade Gaisler and RISC-V's Space Journey
• ITRI and TSMC Collaborate on Advancing High-Speed Computing with SOT-MRAM
• Samsung and TSMC competing to dominate 2nd-gen 3nm at global foundry industry

Tuesday, January 16, 2024

• India's Electric Vehicle (EV) Ecosystem
• Soitec Implements Water Reuse in Wafer Fabs
• How Synopsys' acquisition of Ansys could streamline design and simulation
• Brian Philofsky Joins Flex Logix As Senior Director Of Solutions Architecture
• YorChip, Inc. announces its first Chiplet for Edge AI applications with IP licensed from Semidynamics, the leader in RISC-V IP based in Barcelona
• Innatera shows RISC-V neuromorphic edge AI microcontroller
• OIF Unveils CEI-112G-XSR+-PAM4 Extended Extra Short Reach Implementation Agreement, Paving the Way for Advanced Interconnectivity
• Innatera unveils its groundbreaking ultra-low power neuromorphic microcontroller
• POLYN Announces Agreement with SkyWater Technology to Produce its First Commercial Voice Processing Chip
• BrainChip and MYWAI Partner to Deliver Next-Generation Edge AI Solutions
• NVM Express Announces the Release of the Computational Storage Feature

Tuesday, January 16, 2024

• Andes Announces General Availability of the New RISC-V Out-Of-Order Superscalar Multicore Processor, the AndesCoreâ„¢ AX65

Monday, January 15, 2024

• Video: Leveraging the RISC-V efficient trace (E-Trace) standard
• proteanTecs Launches Power Reduction Solution for High Performance Markets
• Gartner Says Worldwide Semiconductor Revenue Declined 11% in 2023
• Synopsys to Acquire Ansys, Creating a Leader in Silicon to Systems Design Solutions
• Chiplet Makers Expect to Disrupt Incumbents
• MIPS Aims to Give Back Control, for AI-Centric Compute

Sunday, January 14, 2024

• Media Alert: Rambus to Announce Fourth Quarter and Fiscal Year 2023 Results
• Cadence Wins TCSA Top 10 Foreign Sustainable Model Companies Award
• Are Low Carbon Nanomaterials the Key to a Greener Tomorrow?
• Davos: HCLTech CSO Jayaram on Need for Sustainability Speed
• High-bandwidth memory (HBM) options for demanding compute
• Unveiling Sonata: Affordable CHERI Hardware for Embedded Systems
• Crypto Quantique and iMQ to enable quantum secure chip-to-cloud connection
• EnSilica adds Post Quantum Cryptography support to eSi-Crypto IP library
• EdgeCortix Expands Leadership Team with Semiconductor Industry Veteran Tim Vehling as Executive Vice President of Global Sales
• Digital Blocks AMBA Multi-Channel DMA Controller IP Core Family Extends Leadership with releases for core DMA Engines in RISC-V® & ARM® Systems and Peripherals to Memory Applications
• Unveiling a Cutting-Edge 12-bit 5Msps SAR ADC IP Core - Industry-Leading Features, Silicon Proven, and Available for Licensing Now
• Digital Blocks AMBA Multi-Channel DMA Controller IP Core Family Extends Leadership with releases for core DMA Engines in RISC-V® & ARM® Systems and Peripherals to Memory Applications