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Thursday, October 27, 2022

• GUC GLinkâ„¢ Chip Leverages proteanTecs' Die-to-Die Interconnect Monitoring

Wednesday, October 26, 2022

• Cadence Accelerates RF Design with Delivery of New TSMC N16 mmWave Reference Flow
• SiMa.ai Welcomes New Investor MSD Partners Bringing Total Investment to $187 Million - SiMa.ai extends oversubscribed series B1 funding to $67 Million
• Weebit Nano successfully qualifies its ReRAM module
• Blueshift Memory Awarded Innovate UK Smart Grant to Develop AI Computer Vision Module
• Synopsys, Ansys and Keysight Accelerate 5G/6G SoC Designs with New mmWave Reference Flow for TSMC Process Technology
• TSMC Launches OIP 3DFabric Alliance to Shape the Future of Semiconductor and System Innovations
• Report: TSMC stops work on Chinese AI chip amid sanctions confusion
• Siemens partners with TSMC for 3nm product certifications and other technology milestones
• Zynq® UltraScale+™ MPSoC FPGA: REFLEX CES adds a new FPGA version to its Zeus Zynq® UltraScale+™ MPSoC System-on-module
• Cadence Integrity 3D-IC Platform Certified for TSMC 3DFabric Offerings
• Synopsys Collaborates with TSMC to Unleash System Innovation with Most Comprehensive Multi-Die Design Solutions for TSMC's Advanced Technologies
• Cadence's New Flow Automates Custom/Analog Design Migration on TSMC Advanced Technologies
• GUC GLink™ Chip Leverages proteanTecs' Die-to-Die Interconnect Monitoring

Tuesday, October 25, 2022

• Renesas warns on falling semiconductor markets
• Blueshift to demo high speed memory in RISC-V ASIC for computer vision
• Siemens Tessent Multi Die Automates 2.5D and 3D Chip DFT
• Flex Logix EFLX4K eFPGA IP Core on TSMC 7nm Technology Now Available
• GUC Unveils GLink 2.3LL, The World's Most Powerful D2D Interconnect IP Using 2.5D Technology
• IAR Systems' Functional Safety Certified Development Tools for RISC-V support latest SiFive Automotive Solutions
• Worldwide Silicon Wafer Shipments Set a New Record in Q3 2022, SEMI Reports
• Cadence Digital and Custom/Analog Design Flows Achieve Certification for TSMC's Latest N4P and N3E Processes
• More than 50 members join SOAFEE to enable the software-defined vehicle of the future

Tuesday, October 25, 2022

• USB-IF Announces Publication of New USB4® Specification to Enable USB 80Gbps Performance

Tuesday, October 25, 2022

• Analog Bits to Demonstrate Pinless PLL and Sensor IP in TSMC N4 and N5 Processes at TSMC 2022 North America Open Innovation Platform® Ecosystem Forum

Monday, October 24, 2022

• Samsung boosts AI in-memory processing with CXL
• Intel Foundry Services roadmap unveiled one deal at a time
• SiFive and Synopsys Collaborate to Accelerate SoC Design
• Avery Continues to Drive CXL Adoption with New Virtual Platform Features in Support of Version 3.0
• Alphawave IP Achieves Its First Testchip Tapeout for TSMC N3E Process
• Flex Logix Opens Up Licensing to its InferX AI Technology
• Sondrel lists on London Stock Exchange's AIM market
• Rambus Delivers PCIe 6.0 Interface Subsystem for High-Performance Data Center and AI SoCs
• Cadence Reports Third Quarter 2022 Financial Results
• Cadence Joins Intel Foundry Services USMAG Alliance to Accelerate Chip Design Development
• Faraday Reports Third Quarter 2022 Results
• SEGGER introduces streaming trace probe for SiFive RISC-V cores
• Analog Bits to Demonstrate Pinless PLL and Sensor IP in TSMC N4 and N5 Processes at TSMC 2022 North America Open Innovation Platform® Ecosystem Forum

Sunday, October 23, 2022

• Samsung Electronics to Beef up Older Foundry Processes
• Synopsys Advances Designs on TSMC N3E Process with Production-Proven EDA Flows and Broadest IP Portfolio for AI, Mobile and HPC Applications
• Nextera Video and Adeas ST 2110 and NMOS FPGA Cores Receive Latest JT-NM Tested Badges
• Socionext to present its Automotive Expertise at electronica 2022
• Intel Foundry Services Forms Alliance to Enable National Security, Government Applications
• RISC-V Celebrates Upstreaming of Android Open Source Project RISC-V Port
• U.S. Chip Sanctions "Put Temporary Checkmate on China"
• How the CHIPS Act Will Impact Engineers
• Faraday Unveils Design Implementation Services for FinFET Technology Targeting all Foundries

Saturday, October 22, 2022

• TSMC suspends production of powerful GPU chip for Chinese tech firm

Thursday, October 20, 2022

• Wi-Fi 6 and 5G provide today's optimal wireless IoT connectivity
• WiLAN Subsidiaries Enter into License Agreement with Micron
• Agile Analog fast tracks IoT design with macros for analog functions
• Everspin Signs Contract to Provide MRAM IP, Design and Manufacturing Services for Strategic Radiation Hardened FPGA Technology

Wednesday, October 19, 2022

• Marvell Announces Industry's Most Comprehensive 3nm Data Infrastructure IP Portfolio
• CoMira Solutions Expands Global Support

Wednesday, October 19, 2022

• Intrinsic ID Presents Full Range of Chip Security Solutions at TSMC 2022 Open Innovation Platform® Ecosystem Forum

Tuesday, October 18, 2022

• Global 200mm Semiconductor Fab Capacity Projected to Surge 20% to Record High by 2025, SEMI Reports
• SmartDV Achieves ISO 9001:2015 Certification
• NEUCHIPS Secures $20 Million in Series B2 Funding to Deliver AI Inference Platform for Deep Learning Recommendation
• videantis and ADTechnology to build 5nm ADAS/AD SoCs
• USB-IF Announces Publication of New USB4® Specification to Enable USB 80Gbps Performance

Monday, October 17, 2022

• ARM splits out its IoT business
• EnSilica looks to acquisitions, expands Bristol design centre
• TSMC heads below 1nm with 2D transistors at IEDM
• Change drives innovation: New executive assignments at Arm will bring fresh perspectives, renewed focus and growth opportunities
• Intrinsic ID Presents Full Range of Chip Security Solutions at TSMC 2022 Open Innovation Platform® Ecosystem Forum
• Arasan Partners with Testmetrix on its 4.5 GSPS C-PHY / D-PHY HDK and Compliance Test Platform
• VESA Releases DisplayPort 2.1 Specification
• IAR Systems' Functional Safety Certified Development Tools for RISC-V support the latest SiFive Automotive Solutions
• Cadence Expands Collaboration with Samsung Foundry to Advance 3D-IC Design

Monday, October 17, 2022

• proteanTecs Edgeâ„¢ Applications Now Available on the Advantest ACS Solution Store

Sunday, October 16, 2022

• TSMC Reduces Expansion Plan to $36B as Outlook Dims
• 'First' RISC-V CPU certified compliant with ISO 26262
• eInfochips Partners with Taoglas to Offer RF Design Services to Add Wireless Connectivity to Products
• Electronic System Design Industry Hits Record Revenue of Nearly $3.8 Billion in Q2 2022, ESD Alliance Reports
• TSMC Cuts Expansion Plan to $36B as Outlook Sours
• First RISC-V laptop uses Alibaba TH1520 SoC
• Introducing T2M's impressive collection of Silicon Proven, Automotive Grade Interface IP Cores
• MOSCHIP joins TSMC Design Center Alliance
• Andes Announces the N25F-SE Processor, the World First RISC-V CPU IP with ISO 26262 Full Compliance
• Alphawave IP: Q3 2022 Trading and Business Update

Saturday, October 15, 2022

• TSMC delays production of 3nm chips as Samsung Foundry takes process leadership