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Monday, June 27, 2022

• Intel boosts cloud EDA for its foundry business
• Meet Axiomise's Ashish Darbari at DAC to Learn about Benefits of Formal Verification
• New startup MachineWare enables ultra-fast RISC-V simulation
• Synaptics Selects Allegro DVT's VVC Compliance Streams
• SiFive Expands Global Operations, Opens UK R&D Center in Cambridge
• Enhanced Serial Peripheral Interface (eSPI) Master/Slave Controller
• UMC, eMemory, and PUFsecurity Announce Successful Silicon-Proven Secure Embedded Flash IP
• Vayyar Selects proteanTecs to Advance Vehicle Safety with Predictive Analytics
• Flex Logix Hires Barrie Mullins as Vice President of Product Management
• Accenture Announces Intent to Acquire XtremeEDA to Expand Silicon Design Capabilities in Canada and US

Sunday, June 26, 2022

• TSMC Japan 3DIC R&D Center Completes Clean Room Construction in AIST Tsukuba Center
• Ansys Multiphysics Solutions Achieve Certification for TSMC's N3E and N4P Process Technologies
• Flex Logix and CEVA Announce First Working Silicon of a DSP with Embedded FPGA to Allow a Flexible/Changeable ISA
• sureCore's ultra-low memory technologies enable designers to create the reality of the metaverse
• Ansys and TSMC Collaborate to Deliver Multiphysics Design Methodology for Wireless Chips
• IAR Systems enable Visual Studio Code extensions to meet developer demands
• TSMC Japan 3DIC R＆D Center Completes Clean Room Construction in AIST Tsukuba Center
• GbE (10/100/1000 Base-T) PHY IP licensed by 3 different customers in Q2 alone for Worldwide Use

Wednesday, June 22, 2022

• CFX announces commercial availability of anti-fuse OTP technology on 90nm CIS process
• IPrium releases 4-channel ATSC 8VSB Modulator
• Synopsys Completes Acquisition of WhiteHat Security
• Pulsic Enhances Unity Chip Planning Technology with Incremental Floor-planning Capability to Speed IP block Placement, Planning
• Weebit Nano to publicly demonstrate its ReRAM IP module for the first time
• GlobalFoundries Celebrates New Singapore Fab with Arrival of First Tool
• Tortuga Logic Rebrands as Cycuity as It Addresses Evolving Needs in Product Security
• Brite Launches High-Precision 16 bit SAR ADC
• Xiphera receives Business Finland's Young Innovative Company funding

Tuesday, June 21, 2022

• PCI-SIG® Announces PCI Express® 7.0 Specification to Reach 128 GT/s
• Foundry Output Value Up 8% in 1Q22
• RISC-V International emits more open CPU specs
• TSMC Creates Design Options for New 3nm Node
• Intento Design Secures Third Round of Investment to Accelerate Its Commercial Deployment
• MosChip Technologies Appoints Semiconductor Industry Veteran, DVR Murthy As "Vice President of Strategic Initiatives" to Implement and Execute Expanded Solution Offerings
• Codasip adds Veridify secure boot to RISC-V processors
• CEVA Extends its RivieraWaves UWB IP to Support CCC's Digital Key 3.0 Standard for Keyless Access to Vehicles
• M31 Technology has Developed and Validated the Ultra-Low Power 12nm PCIe 5.0 High-Speed Interface IP
• PCI-SIG Announces PCI Express 7.0 Specification to Reach 128 GT/s
• XtremeEDA to enable IoT security deployment with Crypto Quantique's solution using Codasip's RISC-V processor

Monday, June 20, 2022

• Dolphin Design wins an Embedded Award for Tiny Raptor, its Energy-Efficient Neural Network AI Accelerator
• Cadence Announces $100 Million Accelerated Share Repurchase Agreement
• Cadence Achieves PCIe 5.0 Specification Compliance for PHY and Controller IP in TSMC Advanced Technologies
• Expedera Expands Global Reach with New Regional Design Centers and Chinese Langauge Website
• Avery Design Systems PCI Express VIP Enables eTopus SerDes IP and Next-Generation ASIC and Chiplet applications to Achieve Compliance and High-Speed Connectivity
• SiFive Enhances Popular X280 Processor IP to Meet Accelerated Demand for Vector Processing
• Codasip Studio Mac extends potential to design for differentiation with RISC-V
• Codasip L31 customizable RISC-V core is an Embedded World Best in Show
• CV32E40P Core From OpenHW Group Sets the RISC-V Quality Standard For Open-Source Hardware IP
• RISC-V Announces First New Specifications of 2022, Adding to 16 Ratified in 2021
• OPENEDGES to Demonstrate Latest NPU IP, ENLIGHT at CVPR 2022
• Imagination launches IMG RTXM-2200 - its first real-time embedded RISC-V CPU
• OpenHW Group Announces RISC-V-based CORE-V MCU Development Kit for IoT Built with Open-Source Hardware & Software

Sunday, June 19, 2022

• Silicon Topology Joins TSMC Design Center Alliance (DCA)
• VisualSim Antenna System Designer enables simulation of Antenna and Communication Systems
• World's first end-to-end integration of ZKP with FPGAs.
• Fraunhofer IPMS develops CANsec Controller IP-Core CAN-SEC
• Huawei and Nordic cellular IoT licensing deal takes a big step towards industry-wide component-level licensing
• World's First AV1 Decoder Silicon IP with support for 12-bit pixel size and 4:4:4 Chroma Sub-Sampling Released by Allegro DVT
• Complete UFS 3.1 Controller solution (Analog / Digital IP Cores) licensed to China's leading Smartphone Company
• Samsung Ventures invests in Israeli AI systems and semiconductor company NeuReality

Thursday, June 16, 2022

• Embedded World fair: Menta will unveil an unprecedented collaboration with Everspin Technologies
• TSMC FINFLEX™, N2 Process Innovations Debut at 2022 North American Technology Symposium
• Cadence RFIC Solutions Support TSMC N6RF Design Reference Flow
• Synopsys Boosts 5G SoC Development Productivity with New RF Design Flow for TSMC N6RF Process

Wednesday, June 15, 2022

• Siemens extends support of multiple IC design solutions for TSMC's latest processes
• Avery Design Systems Announces Verification Support for New UCIe standard, Accelerating Adoption of Chiplet Interconnect Protocol
• QuickLogic and eTopus Announce Disaggregated, Flexible eFPGA Chiplet Template
• OpenFive Joins Universal Chiplet Interconnect Express (UCIe) Consortium
• Alchip Technologies Offers 3nm ASIC Design Services
• Renesas Develops Circuit Technologies for 22-nm Embedded STT-MRAM with Faster Read and Write Performance for MCUs in IoT Applications
• Cadence Design IP portfolio in TSMC's N5 Process Gains Broad Adoption Among Leading Semiconductor and System Companies
• CAST and Fraunhofer IPMS Mark 20-Year Partnership with Product of the Year Win
• SmartDV Charts Course Toward Chiplets, Joins Universal Chiplet Interconnect Express (UCIe)