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Monday, December 12, 2022

• RISC-V arrives in data centre league
• RISC-V Sees Significant Growth and Technical Progress in 2022 with Billions of RISC-V Cores in Market
• CAES' Quad-Core LEON4FT on its Way to the Moon
• Siemens pioneers commercial grade Linux support for the RISC-V architecture
• CEVA NeuPro-M Edge AI Processor Architecture Recognized at EE Awards Asia 2022
• Intrinsic ID to Showcase its Security Solutions at CES 2023
• NSITEXE Qualifies Imperas RISC-V Reference Models for Akaria Processors NS72A, NS72VA, and NS31A
• Cadence Wins Six 2022 TSMC OIP Partner of the Year Awards
• KI-FLEX AI chip tapes out with flexible videantis processor platform
• Breker Verification Systems Unveils Easy-To-Adopt Integrity FASTApps Targeting RISC-V Processor Core, SoC Verification Scenarios
• Faraday Unveils SONOS eFlash Platform with Infineon on UMC 40uLP
• LeWiz released RISC-V with OmniXtend clustering technology to open source.
• XMOS announces software-defined SoC platform now compatible with RISC-V

Monday, December 12, 2022

• Simon Davidmann President & CEO of Imperas Software elected as Chair of the OpenHW Verification Task Group

Sunday, December 11, 2022

• The sound of joy in your ear
• Quantum-driven IoT security platform available on free trial
• Japan's New Semiconductor Foundry Rapidus Taps IBM For 2nm Process
• Samsung fails to narrow gap with TSMC in foundry market
• MIPS Announces Availability of its first RISC-V IP core - the eVocore P8700 Multiprocessor
• Tata may make chips
• Global Chip Industry Projected to Invest More Than $500 Billion in New Factories by 2024, SEMI Reports
• Codasip launches SecuRISC5 initiative
• MIPS Partners With Mobileye to Accelerate Next Generation Autonomous Driving Technologies and Advanced Driver Assistance Systems
• Imperas releases new updates, test suites, and functional coverage library to support the rapid growth in RISC-V Verification
• QuarkLink scalable IoT Security Platform Now Available on 30-Day Free Trial
• Sofics joins the Intel Foundry Services (IFS) Accelerator IP Alliance program
• USB 3.2 OTG Controller and PHY IP Cores for ultra-high speed, lossless data and power delivery are available for immediate licensing
• BrainChip Joins Intel Foundry Services to Advance Neuromorphic AI at the Edge
• Microchip Showcases RISC-V-Based FPGA and Space-Compute Solutions at RISC-V Summit

Thursday, December 8, 2022

• Soitec CEO remains positive on semiconductor growth
• TSMC November 2022 Revenue Report

Wednesday, December 7, 2022

• Join Andes at RISC-V Summit; Learn the Only ISO 26262 Fully-Compliant RISC-V CPU, the Latest Multicore 4-Way Out-Of-Order Processor & the Multicore 1024-bit Vector Processor
• Apple, AMD Back TSMC's Tripled Investment, Tech Upgrade in Arizona
• Imec enables tight standard cell boundary scaling using a two-level semi-damascene integration scheme
• Imperas and Imagination collaborate on providing virtual platform models for the Catapult RISC-V CPU family
• Siquance: an avant-garde startup dedicated to quantum calculations
• Andes Technology Unveils the AndesCoreâ„¢ D23, a Feature-Rich, Low-Power and Highly-Secured Entry-Level RISC-V Processor
• Imagination PowerVR SDK wins Design Tool and Development Software Product of the Year
• Global Top 10 Foundries' Total Revenue Grew by 6% QoQ for 3Q22, but Foundry Industry's Revenue Performance Will Enter Correction Period in 4Q22, Says TrendForce
• Andes Announces RISC-V Multicore 1024-bit Vector Processor: AX45MPV
• Allegro DVT and V-Nova announce strategic collaboration to accelerate development of LCEVC ecosystem

Tuesday, December 6, 2022

• Samsung and NAVER Collaborate on Chip Solutions for Hyperscale AI
• Intel Pathfinder for RISC-V unifies platform, adds features
• Japan's Rapidus signs up IMEC to support 2nm push
• Andes Technology and Parasoft Collaborate to Provide Seamless Software Testing Tools for Automotive Functional Safety Applications
• MIPS Selects Imperas for Advanced Verification of High-Performance RISC-V Application-class Processors
• Codasip launches Codasip Labs to accelerate advanced technologies
• TSMC Announces Updates for TSMC Arizona

Monday, December 5, 2022

• Finland connects a quantum computer to a supercomputer
• France's Siquance startup targets 'European' quantum computing
• STMicroelectronics and Soitec Partner on SiC Substrate Manufacturing Technology
• Avery Design Systems Announces SimXACT-SAâ„¢ for Improved Sequential X-Verification
• Tachyum Signs MOU with Cologne Chip
• Mixel Patented MIPI D-PHY RX+ IP Integrated into Lumissil Automotive Microcontroller
• Avery Design Systems Announces SimXACT-SA™ for Improved Sequential X-Verification
• Arteris FlexNoC Interconnect Licensed by Telechips for Use in Advanced Automotive Applications
• QuickLogic Inks eFPGA IP Partnership Agreement with Yu-Hsin Layout Technology
• Israeli AI startup NeuReality raises $35M Series A to bring its novel inferencing chip to the market
• IEEE802.11n/ac/ax Wi-Fi LDPC Encoder and Decoder FEC IP Core Available For Licensing and Implementation from Global IP Core
• Lattice Extends Low Power Leadership with New Lattice Avant FPGA Platform
• UMC Reports Sales for November 2022
• Intel Pathfinder for RISC-V: New Capabilities and A Growing Ecosystem

Monday, December 5, 2022

• Xiphera Launches xQlaveâ„¢ Product Family of Quantum-Secure Cryptographic IP Cores

Monday, December 5, 2022

• The Worldwide Semiconductor Market is expected to slow to 4.4 percent growth in 2022, followed by a decline of 4.1 percent in 2023

Sunday, December 4, 2022

• Safety-Aware Chips Serve Automonous-Driving Apps
• Bringing 20/20 Vision to the Edge with AI Inferencing
• Ansys Announces GlobalFoundries Certification of Semiconductor Tools for GF 22FDX® Platform
• Renesas tapes out spiking neural network chip
• Simon Davidmann President & CEO of Imperas Software elected as Chair of the OpenHW Verification Task Group
• Eliyan eliminates silicon interposer to advance D2D chiplet connect for HPC
• Global Semiconductor Sales Decrease 0.3% Month-to-Month in October
• Implement seamless DRAM processing speeds utilizing Silicon Proven DDR4/LPDDR4/DDR3L Combo PHY IP Core in 12FFC process technology
• GUC Monthly Sales Report - November 2022
• Novatek Adopts CEVA's Latest Sensor Hub DSP for New Multi-sensor IP Camera SoC
• Innovative ASIC CPU Drives Record-Setting Server Performance
• Imperas and Andes collaborate to support RISC-V innovations

Saturday, December 3, 2022

• Intel says it will squeeze 1 trillion transistors onto a chip package by 2030

Thursday, December 1, 2022

• Codasip and Intel bring RISC-V development to higher-education
• USB IP Cores for the Intel Pathfinder for RISC-V Platform

Wednesday, November 30, 2022

• Samsung and TSMC Competing to Secure Foundry Customers
• ItoM is now part of the Bosch Group
• CHIPS Alliance Announces Rapid Silicon as its Newest Member
• The Worldwide Semiconductor Market is expected to slow to 4.4% growth in 2022, followed by a decline of 4.1% in 2023
• New Report Identifies Challenges to Continued U.S. Leadership in Semiconductor Design, Innovation
• CEVA Joins Intel Pathfinder for RISC-V Program
• Synopsys Appoints Shelagh Glaser Chief Financial Officer
• Synopsys Posts Financial Results for Fourth Quarter and Fiscal Year 2022
• Global Semiconductor Equipment Billings Increase 9% in Q3 2022, SEMI Reports
• Siemens streamlines medical standards compliance for Linux OS based systems
• Crypto Quantique Joins Silicon Catalyst In-Kind Partner Ecosystem Along with 2 Other UK-based Companies
• Xiphera Launches xQlave™ Product Family of Quantum-Secure Cryptographic IP Cores