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Tuesday, January 31, 2023

• Perfecto by Perforce Releases 2023 State of Test Automation Report
• 4 articles CIOs should read about open source in 2023
• Rambus ups DDR5 data rate and bandwidth by 33%
• UMC and Cadence Collaborate on 3D-IC Hybrid Bonding Reference Flow

Tuesday, January 31, 2023

• Andes Technology Unveils The AndesCore® AX60 Series, An Out-Of-Order Superscalar Multicore RISC-V Processor Family

Monday, January 30, 2023

• Weebit looks forward to first revenue in 2023
• Intel Terminates RISC-V Development Project: What Happened?
• TSMC Joins Hands with Apple and Sony to Keep Samsung in Check
• QuickLogic Partners with Andes Technology for eFPGA Joint Promotion
• Siemens advances integrated circuit verification with new, data-driven Questa Verification IQ software
• Tachyum Successfully Runs UEFI on Prodigy FPGA
• Chiplet Pioneer Eliyan Joins UCIe and JEDEC Industry Standardization Organizations, Expands Veteran Leadership Team to Accelerate Adoption of Breakthrough Die-to-Die Interconnect Solution
• Hardware Root of Trust: The Key to IoT Security in Smart Homes
• Faraday Announces Multi-site Manufacturing Support in ASIC

Sunday, January 29, 2023

• NASA Recruits Microchip, SiFive, and RISC-V to Develop 12-Core Processor SoC for Autonomous Space Missions
• Achieving Unprecedented Power Savings with Analog ML
• U.S. and Japanese Chipmakers Join 2-nm War
• Gidel introduces groundbreaking edge computer with NVIDIA Jetson Orin NX system-on-module and high-bandwidth camera frame grabber for real-time image acquisition compute and AI processing
• Q4 loss at Intel
• EU Parliament Adopts Position on Chips Act
• Linaro to Acquire Arm Forge Software Tools Business
• BrainChip Tapes Out AKD1500 Chip in GlobalFoundries 22nm FD SOI Process
• Intel kills its RISC-V Pathfinder development kit programme
• 10-bit 3Msps Ultra low power SAR ADC IP core for Wireless Communication and Automotive SoCs is available for immediate licensing

Wednesday, January 25, 2023

• BoW Strengthens Pathway to Chiplet Standardization
• Fluent.ai Offers Embedded Voice Recognition for Cadence Tensilica HiFi 5 DSP-Based True Wireless Stereo Products
• Axiomise Accelerates Formal Verification Adoption Across the Industry
• IAR Systems fully supports the brand-new Industrial-Grade PX5 RTOS
• intoPIX to feature TicoXS FIP technology for premium 4K & 8K AVoIP wireless AV at ISE 2023
• Sevya joins TSMC Design Center Alliance
• Cadence Quantus FS Solution, a 3D Field Solver, Achieves Certification for Samsung Foundry's SF4, SF3E and SF3 Process Technologies

Tuesday, January 24, 2023

• Best FPGA (Field-Programmable Gate Arrays) Companies in 2023
• Japan chip venture Rapidus aims for 2-nm prototype line by 2025
• CEA-Leti: innovation to fuel 6G wireless communications
• OpenLogic by Perforce and the Open Source Initiative Release 2023 State of Open Source Report
• Open Compute Project Foundation and JEDEC Announce a New Collaboration
• Avery Design Systems and CoMira Announce Partnership To Enable UCIe-Compliant Chiplet Design
• Weebit Nano nears productisation, negotiating initial customer agreements

Monday, January 23, 2023

• 6G-IA and ETSI to bridge research, standards and industry
• Semiconductor Companies Create Building Block for Chiplet Design
• AI Compute Company Banks on Chiplets for Future Processors
• Startup raises funds to advance neutral atoms quantum computing
• VORAGO Technologies to Move All its Manufacturing Stateside in Strategic Partnership with SkyWater's Trusted Foundry
• Nexperia invests in sustainable alternatives to batteries

Monday, January 23, 2023

• Xiphera announces the first IP core for the quantum-secure xQlaveâ„¢ product family

Monday, January 23, 2023

• The latest ASIL-B,C,D and ISO26262 Certified Silicon Proven Interface IP Cores are ready for immediate licensing

Sunday, January 22, 2023

• Swedish quantum computer boost for industry
• Scaling Up Quantum Computing by Interconnecting Quantum Processors
• New Wave DV Releases Two New SOSA-Aligned 3U VPX ACAP (FPGA) Modules
• Electronic System Design Industry Reports Revenue of $3.8 Billion in Q3 2022, ESD Alliance Reports
• AI Must Be Secured at the Silicon Level
• CEO Interview: Stephen Fairbanks of Certus Semiconductor
• Accellera's Security Annotation for Electronic Design Integration Standard 1.0 Moves Toward IEEE Standardization
• GUC Delivers its First TSMC N3 Chip and First AI-Optimized N5 Design Using Cadence Digital Solutions
• OIF Marks 25th Anniversary, Launches New Physical & Link Layer Working Group Electrical Project and Adds 112G VSR Clause to CEI 5.0 IA at Q1 Technical and MA&E Committees Meeting
• Xiphera announces the first IP core for the quantum-secure xQlave™ product family
• Accellera Announces the Formation of the Clock Domain Crossing Working Group
• The latest ASIL-B,C,D, ISO26262 Certified Silicon Proven Interface IP Cores are ready for immediate licensing

Thursday, January 19, 2023

• Comcores TSN technology and 5G communication expertise to be deployed in a significant EU funded project with pan-European partners