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Tuesday, August 16, 2022

• 48 core neuromorphic AI chip uses resistive memory
• Autotalks Enhances 5G C-V2X Chipsets with proteanTecs Deep Data Analytics
• Credo Launches Comprehensive Family of 112G PAM4 SerDes IP for TSMC N5 and N4 Process Technologies
• OPENEDGES Files Registration Statement for the Initial Public Offering (IPO)
• QuickLogic Reports Fiscal 2022 Second Quarter Results
• BrainChip Empowers Next Generation of Technology Innovators with Launch of the University AI Accelerator Program
• Efinix Low Power, Small Footprint FPGA Selected for SPRESENSE Development Platform
• Alphawave IP is officially 5.0 certified on the PCI-SIG Integrator's List

Monday, August 15, 2022

• Andes Technology and Green Hills Software Team Up to Deliver Advanced Automotive Safety Platform for RISC-V
• Nordic Semiconductor announces its first Wi-Fi chip, the dual-band Wi-Fi 6 nRF7002
• Exclusive CEO Interview: Latest Funding Drives Ventana's First RISC-V Chiplets in Data Centers
• MIPI D-PHY IP Cores along with MIPI DSI Controller IP Cores for both Tx & Rx is available for immediate licensing for high-performance, cost-optimized cameras and displays

Sunday, August 14, 2022

• 2022 RISC-V Taipei Day to be held in September to explore RISC-V driven developments in EV, smart vehicles
• New US EDA Software Ban May Affect China's Advanced IC Design, Says TrendForce
• Edgewater Wireless Expands Intellectual Property Monetization Initiatives
• Intel Elects Lip-Bu Tan to Its Board of Directors

Thursday, August 11, 2022

• Vidatronic Expands Portfolio of Power Management, Analog, and Security IP with Additional 180 nm to 22 nm Technologies for IoT Applications Available for Licensing
• Truechip Announces First Customer Shipment of CXL 3 Verification IP and CXL Switch Model

Wednesday, August 10, 2022

• Neuromorphic Chip Gets $1 Million in Pre-Orders
• Tudor Brown resigns from SMIC
• SMIC Reports 2022 Second Quarter Results
• Opinion: CHIPS Act Escalates Long-Standing U.S.-China Tech Rivalry
• Arasan refreshes its Total USB IP Solution with its next generation of USB 2.0 PHY IP

Wednesday, August 10, 2022

• Cadence Library Characterization Solution Accelerates Delivery and Enhances Quality of Arm Memory Products

Tuesday, August 9, 2022

• Arteris Announces Financial Results for the Second Quarter 2022 and Estimated Third Quarter and Full Year 2022 Guidance
• Siemens selected by Microsoft for Rapid Assured Microelectronics Prototypes (RAMP) Program
• CEVA, Inc. Announces Second Quarter 2022 Financial Results

Monday, August 8, 2022

• Renesas looks to simplify industrial ethernet implementations
• GlobalFoundries CEO: Earnings benefited from balanced supply chain, diverse end markets
• CEVA Celebrates 15 Billionth CEVA-powered Chip Shipped
• Logic Fruit appoints Vijay Pal Sharma as VP - Engineering

Sunday, August 7, 2022

• SiFive Is Leading The Way For Innovation On RISC-V
• GlobalFoundries and Qualcomm Announce Extension of Long-term Agreement to Secure U.S. Supply through 2028
• Space Codesign Systems joins Siemens Digital Industries Software Solution Partner Program as a Software and Technology Partner
• Arm achieves record revenue and shipments in Q1 FY 2022
• Enhance your SD Card experience by integrating SD 4.1 UHS-II PHY IP Core to achieve Ultra High Speeds

Thursday, August 4, 2022

• Intel tGPU Setback Expected to Slow TSMC's 3 nm Ramp
• Nordic Semi sets up RISC-V design team
• Brite Semiconductor provides xSPI/Hyperbusâ„¢/Xcellaâ„¢ controller and PHY total solution
• Brite Semiconductor provides xSPI/Hyperbus™/Xcella™ controller and PHY total solution
• GUC Monthly Sales Report - July 2022
• Cadence Accelerates Hyperscale SoC Design with Industry's First Verification IP and System VIP for CXL 3.0