MIPI C-PHY v1.0 D-PHY v1.2 RX 2 trios/2 Lanes in TSMC (12nm, N5)
ESL Design Articles
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Efficient creation of peripheral simulation from specifications (Jun. 05, 2006)
In this paper, we discuss a method of efficiently constructing peripheral simulation models from simple & easy-to-use representations.
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Automated video algorithm implementation (Jun. 02, 2006)
This article presents an overview of a C-based design flow that enables designers to generate high-quality hardware for video algorithms. Algorithmic C synthesis is used to generate optimized RTL from algorithmic specification written in pure ANSI C++
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A bridging model for ESL synthesis (May. 30, 2006)
SystemC has recently become popular for electronic system-level (ESL) modeling because of the growing complexity of systems on a chip (SoCs), and because of the ubiquity of C and C++. It facilitates the incorporation of embedded software, instruction set
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A SystemVerilog DPI Framework for Reusable Transaction Level Testing, Debug and Analysis of SoC Designs (May. 22, 2006)
This paper describes a transaction based framework for reusing tests and modeling based on inter-language function calls (ILFC) using SystemVerilog DPI (Direct Programming Interface) [1] and C
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Sequential equivalence checking supports ESL flow (May. 15, 2006)
The complexity of digital-signal-processing-oriented applications is continually increasing. In the past, our group in STMicroelectronics developed our own Matlab-to-RTL design and verification methodology.
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SystemVerilog reference verification methodology: RTL (May. 01, 2006)
Verification remains the single biggest challenge in the design of system-on-chip (SoC) devices and reusable IP blocks. As designs continue to grow in size and complexity, new techniques emerge that must be linked by an effective methodology for significa
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Implementation of a SystemC Assertion Library (Apr. 10, 2006)
We propose a native SystemC assertion library which is designed in a similar fashion to the OVL, in order to enable assertion based verification especially for system level designs and IP-integration verification in SystemC. Each assertion is implemented
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SystemVerilog reference verification methodology: Introduction (Mar. 27, 2006)
This is the first in a series of four articles outlining just such a solution: a reference verification methodology enabled by the SystemVerilog hardware design and verification language standard. This methodology is documented in a comprehensive book — t
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Managing Complexity with SystemC (Mar. 09, 2006)
This paper is an attempt to look at a more holistic approach to using SystemC for modeling. It is also attempts to expose the latent strengths of the SystemC framework that could be exploited in modeling systems.
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The 'what' and 'why' of transaction level modeling (Feb. 27, 2006)
Transaction level models (TLMs) can help with design, integration and verification issues associated with large, complex systems. TLMs allow designers to model hardware at a higher level of abstraction, helping to smooth the integration process by providi
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ESL Requirements for Configurable Processor-based Embedded System Design (Jan. 30, 2006)
This paper briefly surveys ESL and IP-based design, outlines the requirements for supporting design with multiple configurable, extensible processors, and sketches the characteristics of possible solutions
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Integrating a Multi-Vendor ESL-to-Silicon Design Flow Using SPIRIT (Jan. 16, 2006)
In this paper, we will show how SPIRIT standard is helping to close the gulf between ESL design exploration environments and the SoC implementation flows
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Using software synthesis for multiprocessor OS and software development (Jan. 06, 2006)
As John Hennessey, founder of MIPS Technologies and president of Stanford University, has pointed out, writing a program on a chip to run a word processor is a lot easier than creating a state machine to do it.
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Using SystemVerilog for functional verification (Dec. 05, 2005)
The need to improve functional verification productivity and quality continues to grow. The 2004/2002 IC/ASIC Functional Verification Study, by Collett International Research, shows that logic or functional errors are the leading cause of ASIC respins (Fi
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Performing rapid and safe evaluations at the architectural level (Nov. 16, 2005)
A new approach that gives designers the tools to tackle changes quickly and safely at the architectural level while staying close to the hardware implementation.
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Designing hardware with C-based languages (Nov. 14, 2005)
To ensure a faster path to success when designing hardware with C-based languages, here is a short list of items that require attention.
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Using PLDs for Algorithm Acceleration - Faster, Better, Cheaper (Aug. 31, 2005)
By combining programmable logic and ESL design tools, certain algorithms gain faster performance at lower clock speeds at less power.
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Performances Estimation Metamodel for MDA Based SoC Design (Aug. 29, 2005)
we present a novel methodology permitting SoC design from high abstraction levels specification, based on the Model Driven Architecture approach (MDA)
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Functional Transaction Level Modeling simplifies heterogeneous multiprocessor software development (Aug. 22, 2005)
By Filip Thoen, Virtio
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A SystemC based Virtual Prototyping Methodology for Embedded Systems (Aug. 10, 2005)
This paper outlines the virtual prototyping methodology originally developed to help define and implement handheld RF based embedded systems
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ESL enables software-driven SoCs (Jul. 25, 2005)
Electronic system-level (ESL) design is a set of methodologies that enables SoC engineers to efficiently develop, optimize and verify complex system architectures and embedded software
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Using SystemVerilog Assertions in RTL Code (Jul. 18, 2005)
SystemVerilog Assertions are not difficult to learn; in this tutorial, you will learn the basic syntax, so that you can start using them in your RTL code and testbenches.
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Electronic system-level development: Finding the right mix of solutions for the right mix of engineers (Jun. 06, 2005)
Electronic system-level development: Finding the right mix of solutions for the right mix of engineers
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Advancing Transaction Level Modeling -- Linking the OSCI and OCP-IP Worlds at Transaction Level (Apr. 01, 2005)
Advancing Transaction Level Modeling -- Linking the OSCI and OCP-IP Worlds at Transaction Level
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Breathing life into hardware and software codesign (Mar. 16, 2005)
Breathing life into hardware and software codesign
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Doing ESL design: the earlier, the better (Mar. 14, 2005)
Doing ESL design: the earlier, the better
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Design of SystemVerilog Assertion IP (Mar. 11, 2005)
Design of SystemVerilog Assertion IP
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Turning software into hardware (Mar. 02, 2005)
Turning software into hardware
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ESL to drive design automation markets (Feb. 10, 2005)
ESL to drive design automation markets
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VUPU: Configurable Processor for C Level Design (Jan. 11, 2005)
VUPU: Configurable Processor for C Level Design