D&R Industry Articles

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How to use snakes to speed up software without slowing down the time-to-market?

At BitSim, we have a way to simplify and speed up the development cycle. In this document, we will discuss the issue of network load in an IoT environment as well as "our" way to speed up the development.

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Testing Of Repairable Embedded Memories in SoC: Approach and Challenges

This article focuses on how to test repairable memories when we include the repair feature, and it will also look at how it will be affected during Automatic Test Pattern Generation (ATPG) or built-in pattern generation. In addition, it focuses on the common challenges and includes a comparative case study on enabling and disabling BIRA features in memories.

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SoC Interconnect: Don't DIY!

With so many acquisitions in the interconnect IP market, you might be forgiven for thinking DIY interconnect is a good idea.

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Extending RISC-V ISA With a Custom Instruction Set Extension

RISC-V ISA (Instruction Set Architecture) is designed in a modular way. It means that the ISA has several groups of instructions (ISA extensions) that can be enabled or disabled as needed. This allows implementing precisely the instruction groups that the application needs, without having to pay for area or power that will not be used.

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Dual Mode C-PHY/D-PHY: Enabling Next Generation of VR Displays

For many years, Virtual Reality (VR) and Augmented Reality (AR) were strongly linked to gaming and entertainment applications. Today, the VR/AR and their combined version, Mixed Reality (MR), have their applications extended to other domains like healthcare, military, education, manufacturing, retail, marketing and advertising. What are the challenges for next generation VR displays? What makes the MIPI interfaces the best fit for VR/AR/MR applications?