D&R Industry Articles

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Power Management for Internet of Things (IoT) System on a Chip (SoC) Development

There are many factors that must be considered when developing a custom System on a Chip (SoC) for Internet of Things (IoT) applications. Chief among these are the power management circuits on the die. Vidatronic offers this white paper to discuss these considerations and all of the various circuit blocks that can be found in this application. Vidatronic IP solutions are discussed and the benefits they bring to IoT SoC designers.

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Reduce Time to Market for FPGA-Based Communication and Datacenter Applications

As FPGA-based realizations become bigger and more complex, synthesis tools that deliver an automated flow are the obvious choice for creating optimized designs in a timely manner.

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Designing for safety and security in a connected system

Good embedded software has always been designed for both safety and security. However, connectivity has introduced intolerable levels of security vulnerability in safety-critical applications such as medical, autonomous vehicles, and Internet of Things (IoT) devices.

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The case for integrating FPGA fabrics with CPU architectures

Physics restricts how much further process geometry shrinkage can take us in terms of boosting processor throughput.

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Addressing Clock Tree Synthesis Challenges

Clock tree synthesis (CTS) plays an important role in building well-balanced clock tree, fixing timing violations and reducing the extra unnecessary pessimism in the design. The goal during building a clock tree is to reduce the skew, maintain symmetrical clock tree structure and to cover all the registers in the design. We have captured some problematic scenarios and the problem solving approaches in this article.

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UVM Sequence Library - Usage, Advantages, and Limitations

Increasing size and complexity of designs and systems have made it mandatory to randomize the stimulus driven to these designs, as directed scenarios will take more time to complete the verification. Along with randomization, there is a need of same design code to be exercised multiple times, this is achieved through multiple simulations of same test sequence. The test sequence will include the feature specific randomization. During multiple runs of test sequence, the randomization will provide different stimulus for design.