D&R Industry Articles

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PUF: A Crucial Technology for AI and IoT

One of the key challenges for AIoT is the protection of AI assets. AI functions often need to detect, evaluate and respond in real time. As a result, a critical security concern is the fact that internal databases and interfaces for AI are not suitable for encryption because such an operation would demand too much time and resources.

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IP Security Assurance Standard

This paper introduces an emerging new standard called IP Security Assurance (IPSA) to address these concerns in a manner that is low-overhead, non-disruptive, and scalable across IP families. The standard specifies an approach to highlight IP assets and associated entries in the Common IP Security Concerns Enumeration (CIPSCE) knowledge base for the mitigation implementer to address.

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How to Design SmartNICs Using FPGAs to Increase Server Compute Capacity

An FPGA-based SmartNIC employs the expanded hardware programmability of FPGAs to build any data-plane functions required by the tasks offloaded to the SmartNIC. Because FPGAs are reprogrammable, the data-plane functions implemented by the FPGA can be torn down and reconfigured at will and in real time. All such offloaded functions operate at hardware – not software – speeds.

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The Age of the Monster Chip

What are the system designs that require a leap in SoC complexity? It's not only big datacenter artificial intelligence (AI) chips, but also autonomous vehicles such as cars, trucks and drones; they are self-landing, reusable rockets; they are medical devices carrying out remote diagnostics.

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Better Benchmarks through Compiler Optimizations: Codasip Jump Threading

The architectural efficiency of embedded processor IP is measured by a small set of industry standard benchmarks, that even though often bear little correlation to real workloads, continue to persist. The most popular benchmarks are Dhrystone and CoreMark.

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UVM RAL Model: Usage and Application

To cope with the speed of the competitive market landscape, most of the systems are designed in a generic way - which means the same design can be used in different ways with different configurations. More the number of configurations, more the number of registers in the design.

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Re-Architecting SoCs for the AI Era

This paper will define AI, describe its applications, the problems it presents, and how designers can address those problems through new and holistic approaches to SoC and network on chip (NoC) design. It also describes challenges implementing AI functionality in automotive SoCs with ISO 26262 functional safety requirements.

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Improving design routability and timing by smart port reduction and placement technique

The design complexity of sub-micron designs due to ever growing huge number of gates and interactions has made it difficult for physical design tools to handle the physical synthesis or placement and routing of such SOCs. Hence design partitioning plays a critical role for implementation of such design which deploys divide-and-conquer strategy.