D&R Industry Articles

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DDR IP Hardening - Overview & Advance Tips

DDR is most critical IP to SoC’s successful operation, because processors in SoC typically spends the majority of its cycles on reading and writing to DDR memory.

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At the edge of data processing

Neural networks’ data processing raises several challenges in terms of performance requirements. Therefore, the cloud was the first location to host this large processing demand, but this is currently evolving .

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Part 2: Opening the 5G Radio Interface

Carriers are now deploying 5G across the globe driven by the need to keep up with relentless mobile data growth. 5G New Radio (NR) operates at higher frequencies to increase bandwidth, but at the expense of range. There will therefore be a need for a much larger number of 5G RUs to provide the same coverage. The availability of cost-effective, reliable and open 5G radio units is therefore critical.

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Why VAD and what solution to choose?

More than ever before, the attention to power consumption is paramount when developing new products. In this environment, voice activity detection has a major role to play for any new voice-controlled system.

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Analog and Power Management Trends in ASIC and SoC Designs

The design of modern Application Specific Integrated Circuits (ASICs) and Systems on a Chip (SoCs) in advanced process nodes can be differentiated by the on-die integration of analog functions, such as power management. Vidatronic offers this white paper to give some historical background on this trend and delve specifically into the integration of power management. Vidatronic IP solutions and the benefits they bring to ASIC and SoC designers are discussed.

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Where Innovation Is Happening in Geolocation. Part 1: Signal Processing

At first glance, geolocation technology seems to work well. Our phones and cars get us to where we need to be with little effort and rather reliably. For consumers, it’s a free service, thanks to service providers like Google and Apple.

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GRSCRUB: FPGA Configuration Supervisor

The GRSCRUB is an external Field Programmable Gate Array (FPGA) configuration supervisor developed by Cobham Gaisler as an Intellectual Property (IP) core. The GRSCRUB IP features different capabilities, such as programming and scrubbing, which prevents the accumulation of errors in the configuration memory of SRAM-based FPGAs.