D&R Industry Articles

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SRAM PUF is Increasingly Vulnerable

As semiconductor technology advances, SRAM is becoming outmoded as a reliable PUF security solution.

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Layout versus Schematic (LVS) Debug

In ASIC physical implementation, once layout is generated, it must follow all the design rules for successful manufacturing and must match the schematic of the required design. To ensure this in physical verification, Design Rule Check (DRC) is carried out to check whether the layout follows the rules for fault-less manufacturing or not.

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Choosing the Right IP for Die-to-Die Connectivity

Higher data rates and more complex functionalities are increasing the SoC size for hyperscale data center, AI, and networking applications.

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Interface Timing Challenges and Solutions at Block Level

In this article, we will address the challenges faced while fixing the interface timing and the solutions to overcome these challenges. We have used Cadence Innovus as our PnR and Synopsys Primetime as our Sign-off timing tool.

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Setup Margin Aware Quick Hold Fixing

Static Timing Analysis (STA) is a key factor to validate while manufacturing a chip, where each design must go for setup and hold validation. In today’s era, technology nodes are shrinking and crosstalk plays a major role in timing along with cell-net delay. In addition, accounting derate (OCV/AOCV/POCV) is to overcome PVT uncertainties of the chip.

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Securing Smart Connected Homes with OTP NVM

The market for piracy is huge and hackers have become increasingly sophisticated even when security is implemented in hardware. The race between the aggressors and protectors is a battle without end. Smart connected home devices are increasingly storing and processing very sensitive and private user data in addition to attempting to deliver copyright protected content from service providers. Protecting consumer data is vital.

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Why the Memory Subsystem is Critical in Inferencing Chips

The number of new inferencing chip companies announced this past year is enough to make your head spin. With so many chips and no lack of any quality benchmarks, the industry often forgets one extremely critical piece: the memory subsystem. The truth is, you can’t have a good inference chip unless you have a good memory subsystem.