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MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
D&R Industry Articles
Articles for the Week of November 28, 2022
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Is your career at RISK without RISC-V?
I am delighted to share my technical insights into RISC-V in this article to inspire and prepare the next generation of chip designers for the future of the open era of computing. If you understand how we build complex electronic devices like desktops and smartphones using processors, you would be more interested in learning and exploring the Instruction Set Architectures.Articles for the Week of November 21, 2022
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Right Python Framework Selection for Automation Testing
Test automation is the practice of automating test execution using frameworks and tools to carry out tests more quickly and reduce the need for human testers. In this method of software testing, reusable test scripts are created to test the functioning of the application, cutting down on overall regression time and facilitating quicker software releases.- Weighing Chip-Design-Verification Challenges for MedTech
- Using edge AI processors to boost embedded AI performance
- How Low Can You Go? Pushing the Limits of Transistors - Deep Low Voltage Enablement of Embedded Memories and Logic Libraries to Achieve Extreme Low Power
Articles for the Week of November 14, 2022
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Efficient Verification of RISC-V processors
Processor verification, however, is never trivial but requires combining the strengths of multiple verification techniques. This technical paper considers how to efficiently verify a RISC-V processor using a multi-layered approach known as the Swiss cheese model adapted from the world of avionics.Articles for the Week of November 7, 2022
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Put a Data Center in Your Phone!
Datacenters heavily leverage FPGAs for AI acceleration. Why not do the same for low power edge applications with embedded FPGA (eFPGA)?Articles for the Week of October 31, 2022
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Driving ADAS Applications with MIPI CSI-2
We’re all familiar with seeing social media influencers on our mobile phones these days, but when you think about it, the real influencers are the mobile phones themselves. Over the past decade, as mobiles have evolved and pushed all sorts of technological boundaries, they have influenced other industries to follow suit.Articles for the Week of October 24, 2022
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Compute Express Link 3.0
Compute Express Link™ (CXL™) is an open industry standard interconnect offering high-bandwidth, low-latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O devices.Articles for the Week of October 17, 2022
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Arteris System IP Meets Arm Processor IP
The design of system-on-chip (SoC) devices for automotive applications—and the reuse of portions of those designs for future SoC incarnations—just got a lot easier with the recent announcement of the expanded partnership between Arm and Arteris.Articles for the Week of September 26, 2022
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Interlaken: the ideal high-speed chip-to-chip interface
As data consumption grows and chip designs evolve to meet this demand, Interlaken is the ideal high-speed chip-to-chip interface with efficiency, reliability and scalability.Articles for the Week of September 19, 2022
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MACsec for Deterministic Ethernet applications
Why MACsec is a compelling security solution for Deterministic Ethernet networks and how Packaged Intellectual Property solutions can accelerate time-to-market for chip developersArticles for the Week of September 12, 2022
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Multi Voltage SoC Power Design Technique
Minimizing power consumption is a major factor that contributes to the modern-day development of IC designs, especially in the consumer electronics segment.Articles for the Week of September 5, 2022
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How to accelerate memory bandwidth by 50% with ZeroPoint technology
Digitalization quickly accelerates energy consumption and is projected to stand for more than one-fifth of global electricity demand by 2030. This makes "performance per watt" critical. ZeroPoint technology for microchips delivers up to 50% more performance per watt by removing unnecessary information.