D&R Industry Articles

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When Traceability Catches What Verification Does Not

Through a complex design process, some mistakes will inevitably slip by even the most expert system-on-chip (SoC) design teams. A disciplined V-model process (diagrammed below) will guard against many of these errors in the concept-to-design process (left arm) and in the verification-to-validation process (right arm).

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Stop-For-Top IP model to replace One-Stop-Shop by 2025... and support the creation of successful Chiplet business

The One-Stop-Shop model has allowed IP vendors of the 2000’s to create a successful IP business, mostly driven by consumer application, smartphone or Set-Top-Box. The industry has dramatically changed, and in 2020 is now driven by data-centric application (datacenter, AI, networking, HPC…), requiring best-inclass, high performance IP developed on bleeding edge technology nodes.

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Understanding Interface Analog-to-Digital Converters (ADCs) with DataStorm DAQ FPGA

We propose the implementation of analog signals into digital signals and data communication between the ADC and FPGA (Field Programmable Gate Array). For working on the ADC, we have used the “DataStorm DAQ” FPGA board. Designers can use any type of FPGA.

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The pitfalls of mixing formal and simulation: Where trouble starts

The most effective functional verification environments employ multiple analysis technologies, where the strengths of each are combined to reinforce each other to help ensure that the device under test (DUT) behaves as specified.

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An 800 Mpixels/s, ~260 LUTs Implementation of the QOI Lossless Image Compression Algorithm and its Improvement through Hilbert Scanning

This paper discusses the hardware implementation of an encoder and a decoder for the QOI lossless RGB image format. Some results are given for the AMD/Xilinx architecture, reaching over 800 Mpixels/s in Ultrascale+ and more than 4K@30 in Artix-7. A compression improvement up to ~15% is also observed when natural images are scanned along a Hilbert curve instead of the normal raster order.

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FPGA Market Trends with Next-Gen Technology

Due to their excellent performance and versatility, FPGAs (Field Programmable Gate Arrays) appeal to a wide spectrum of businesses. Also, it has the feature of adopting new standards and modifying hardware as per the specific application requirement even after it’s been deployed for usage

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Add Security And Supply Chain Trust To Your ASIC Or SoC With eFPGAs

Even though there are many security and encryption techniques designers can use to make a chip secure, what else can be done to increase the confidence that the chip is trustworthy? eFPGA opens a new range of capabilities

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Capitalizing on the Architectural Flexibility of FPGAs with RISC-V and a Simplified Programming Flow

Microprocessors have traditionally dominated the realm of computing, and in this drive toward more compute capabilities, silicon-based ICs were consistently improved upon in device density

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Why Hardware Root of Trust Needs Anti-Tampering Design

The hardware root of trust (HRoT) provides the trust base (root key), hardware identifier (UID), hardware unique key (HUK), and entropy required for the secure operation of the entire chip and therefore is often the focus of hacker attacks. If the design can’t effectively resist attacks, hackers can easily obtain the secrets of the entire chip. Attackers can use the secrets to crack identity authentication and data encryption and steal product design know-how, causing application security problems.