D&R Industry Articles

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Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

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Understanding Efficiency of Switched Capacitor DC-DC Converters for Battery-Powered Applications

This application note provides a brief theory on the efficiency in SC DC-DC converters and a comparative efficiency analysis between the two types of switched converter architectures using a typical application case.

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Creating Domain Specific Processors Using Custom RISC-V ISA Instructions

When System-on-Chip (SoC) developers include processors in their designs, they face choices in solving their computational challenges. Complex SoCs will usually have a variety of processor cores responsible for varied functions such as running the main application programs, communications, signal processing, security, and managing storage.

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Reducing Debug time for Scan pattern using Parallel Strobe Data (PSD) Flow

With the increasing complexity in design in the semiconductor industry and advanced lower technology nodes, it is important as a DFT architecture design and service engineer to signoff the chip with timing simulation for all sets of the patterns generated by ATPG tool before it goes for manufacturing.

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PUF based Root of Trust PUFrt for High-Security AI Application

This article will discuss how to strengthen the security of AI systems from the structure of the AI hardware device, to the security requirements, solutions, and etc. To do this, we will use PUFsecurity’s hardware root of trust module, PUFrt, as an example to help readers understand how combining AI application architecture and physical unclonable function (PUF) can benefit hardware security technology.

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RISC-V's CPU Verification Challenge

RISC-V is new and does not have the benefit yet of years of field-proven experience. This means that a carefully chosen and executed CPU verification strategy is essential. It also means that the availability of a “golden reference model” is a critical component that must be secured.

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How a voltage glitch attack could cripple your SoC or MCU - and how to securely protect it

Hackers and criminals have an array of techniques available to them to intrude into, tamper with, disable or destroy electronics products and services. Some of the techniques are invasive, and call for very expensive equipment and deep engineering expertise to analyze and modify nanoscale electronics circuitry.

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Optimization of Crosstalk Delta Delay on Clock Nets

In this paper, we would analyse the causes of high crosstalk delta delay on clock nets and find an automated way to take care of the crosstalk delta by applying single-width double-track NDR on clock nets at an early stage of the design cycle.