D&R Industry Articles

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Increase battery life of Consumer Products using architecture simulation

For a consumer application, the response time, display resolution and battery life are the top features. The lifecycle of the battery is directly proportional to its capacity, power spikes and usage profile. The battery size cannot be increased indiscriminately because of cost, space and reliability considerations.

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Distorted Waveform Phenomena in 7nm Technology Node and its Impact on Signoff Timing Analysis

In today’s deep sub-micron technology nodes like 16nm, 7nm & beyond, there is a huge challenge for accurate static timing calculation. Ever increasing routing congestion, thin metal layers and moreover very high speed signal propagation make these nodes prone to significant crosstalk effects.

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It's Not My Fault! How to Run a Better Fault Campaign Using Formal

The ISO 26262 automotive safety standard requires evaluation of safety goal violations due to random hardware faults to determine diagnostic coverages (DC) for calculating safety metrics. Injecting faults using simulation may be time-consuming, tedious, and may not activate the design in a way to propagate the faults for testing. With formal verification, however, faults are easily categorized by structural analysis providing a worst-case DC.

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Image Processing - RTL Implementation of Median Filtering for Image Denoising

This article explains step by step implementation of Median Filtering Algorithm in Verilog. This filtering technique is then applied to noisy image for denoising. This article also explains simple Verilog based testbench and Matlab scripts for image pre/post processing operation for verifying the same.

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Creating SoC Integration Tests with Portable Stimulus and UVM Register Models

In this article, we will explore how portable stimulus, via Accellera’s Portable Stimulus Standard (PSS), can leverage information captured in a register model to automate creation of block, subsystem, and SoC register-access tests.

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Memory Testing - An Insight into Algorithms and Self Repair Mechanism

Conventional DFT methods do not provide a complete solution to the requirement of testing memory faults and its self-repair capabilities. A promising solution to this dilemma is Memory BIST (Built-in Self-test) which adds test and repair circuitry to the memory itself and provides an acceptable yield. This article seeks to educate the readers on the MBIST architecture, various memory fault models, their testing through algorithms, and memory self-repair mechanism.

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Signoff Iteration Reduction Technique for Fixing Top Level Antenna

While developing large-sized chips, “divide & conquer” techniques are used. This involves partitioning the design, implementing each block individually, and stitching them together at the top level. Even if the blocks are all clean with respect to physical and timing signoff, they show incremental violations when they are stitched together.

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A Heuristic Approach to Fix Design Rule Check (DRC) Violations in ASIC Designs @7nm FinFET Technology

The intent of this paper is to explain the varied kinds of DRCs (Design Rule Checks) that are encountered in the Physical Design flow. This paper will discuss the Metal DRC violations (7nm Technology) generally seen at the block level and outline the practical approach to fix them.

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How to achieve low latency audio/video streaming over IP network

This whitepaper will first define the latency for audio/video transport. It will highlight the usual architecture challenges of an AV over IP transmitter/receiver. A deeper analysis is provided regarding the video compression which is often mistakenly considered as adding too much latency. Eventually, actual latency measurements of the Viper 4K HDMI to IP transmitter/receiver will be presented.