English
| |
20 Most Popular Articles
Updated: Thu, 19 Apr 2018 01:00:01 +0200
|
Today |
Yesterday |
||
| 1 | 1 |
Dynamic Memory Allocation and Fragmentation in C and C++ In C and C++, it can be very convenient to allocate and de-allocate blocks of memory as and when needed. This is certainly standard practice in both languages and almost unavoidable in C++. However, the handling of such dynamic memory can be problematic and inefficient. For desktop applications, where memory is freely available, these difficulties can be ignored. For embedded - generally real time - applications, ignoring the issues is not an option. |
|
| 2 | 2 |
A Review Paper on CMOS, SOI and FinFET Technology In 1958, the first integrated circuit flip-flop was built using two transistors at Texas Instruments. The chips of today contain more than 1 billion transistors. The memory that could once support an entire company’s accounting system is now what a teenager carries in his smartphone. This scale of growth has resulted from a continuous scaling of transistors and other improvements in the Silicon manufacturing process. |
|
| 3 | 3 |
How to calculate CPU utilization How to calculate CPU utilization |
|
| 4 | 4 |
Using SystemVerilog Assertions in RTL Code SystemVerilog Assertions are not difficult to learn; in this tutorial, you will learn the basic syntax, so that you can start using them in your RTL code and testbenches. |
|
 |
5 | 8 |
Method for Booting ARM Based Multi-Core SoCs In the boot process various modules/peripherals (like clock controller or security handing module and other master/slaves) initialized as per the SoC architecture and customer applications. In Multi core SoCs, first primary core (also called booting core) start up in boot process and then secondary cores are enabled by software. |
 |
6 | 5 |
FPGA programming step by step FPGA programming step by step |
|
7 | 6 |
PCIe error logging and handling on a typical SoC This paper details first PCIe errors, error logging and then the error handling on a typical SoC. |
|
8 | 7 |
Design Rule Checks (DRC) - A Practical View for 28nm Technology The main objective of this paper is to explain the various types of design rule checks (DRC) violation, their causes and how to fix the various design rule checks (DRC) at lower technology node on block level as well as full chip level implementation while meeting the design rule with respect to latest technology standards. |
| 9 | 9 |
Understanding - and Reducing - Latency in Video Compression Systems In the video world, latency is the amount of time between the instant a frame is captured and the instant that frame is displayed. Low latency is a design goal for any system where there is real-time interaction with the video content, such as video conferencing or drone piloting. |
|
|
10 | New!!! |
Design Considerations for High Bandwidth Memory Controller High Bandwidth Memory (HBM) is a high-performance 3D-stacked DRAM. It is a technology which stacks up DRAM chips (memory die) vertically on a high speed logic layer which are connected by vertical interconnect technology called TSV (through silicon via) which reduces the connectivity impedance and thereby total power consumption. |
|
11 | 12 |
FPGA Implementation of AES Encryption and Decryption This paper presents a high speed, fully pipelined FPGA implementation of AES Encryption and Decryption (acronym for Advance Encryption Standard, also known as Rijndael Algorithm) which has been selected as New Algorithm by the National Institutes of Stand |
|
12 | New!!! |
Design Rule Violation fixing in timing closure Design Rule violation is one of the major challenges being faced by VLSI industry. With ever shrinking technology nodes, and ever increasing gate counts, reaching to more than 40 million on a single die, the complexity of the design is momentous! |
|
13 | New!!! |
Power Management for Internet of Things (IoT) System on a Chip (SoC) Development There are many factors that must be considered when developing a custom System on a Chip (SoC) for Internet of Things (IoT) applications. Chief among these are the power management circuits on the die. Vidatronic offers this white paper to discuss these considerations and all of the various circuit blocks that can be found in this application. Vidatronic IP solutions are discussed and the benefits they bring to IoT SoC designers. |
| 14 | 14 |
Easier UVM Sequences - SystemVerilog UVM Sequence and Task Equivalence SystemVerilog UVM sequences are a powerful way to model stimulus and response for functional verification. Unfortunately using SystemVerilog UVM sequences can require an extensive background in SystemVerilog, the UVM and object oriented programming. This paper explains a collection of techniques to allow the power of sequences with familiarity and simplicity of calling tasks. |
|
|
15 | 17 |
Multi-Gigabit SerDes: The Cornerstone of High Speed Serial Interconnects by Jerry C. Chen -- Genesys Logic America, Inc. |
|
16 | New!!! |
A comparison of Network-on-Chip and Busses This whitepaper summarizes the limitations of traditional bus-based approaches, introduces the advantages of the generic concept of NoC, and provides specific data about Arteris’ NoC, the first commercial implementation of such architectures |
|
17 | New!!! |
NAND Flash memory in embedded systems This paper presents fundamental information about NAND Flash memory used in Embedded Systems. It discusses various aspects of this storage media such as interface, architecture, error source and error correction as well as software required for building application. |
|
18 | 15 |
Power analysis of clock gating at RTL In this article, we will discuss the use of clock gating techniques with design examples for achieving lower power and also highlight the impact of clock gating on different areas of the design process like metastability with clock domain crossings and testability. The article also details the do's and don'ts of clock gating to avoid chip failures and unnecessary power dissipation. |
|
19 | New!!! |
Why using Single Root I/O Virtualization (SR-IOV) can help improve I/O performance and Reduce Costs In this paper, we will explore why designing systems that have been natively built on SR-IOV-enabled hardware may be the most cost-effective way to improve I/O performance and how to easily implement SR-IOV in PCIe devices. |
|
20 | 11 |
CORTEX-R versus CORTEX-M Cortex-R and cortex-M series is targeted for different requirements and for different applications. It is important to know the parameters and features that separates them as there could be applications where both of them can fit in. This paper is targeted for such a scenario and helps the Designers for selection. The final objective is to help the Designers or Developers to have understanding of Architectures of ARM. |
