English
| |
20 Most Popular Articles
Updated: Sat, 15 Dec 2018 01:00:01 +0100
|
Today |
Yesterday |
||
| 1 | 1 |
Dynamic Memory Allocation and Fragmentation in C and C++ In C and C++, it can be very convenient to allocate and de-allocate blocks of memory as and when needed. This is certainly standard practice in both languages and almost unavoidable in C++. However, the handling of such dynamic memory can be problematic and inefficient. For desktop applications, where memory is freely available, these difficulties can be ignored. For embedded - generally real time - applications, ignoring the issues is not an option. |
|
| 2 | 2 |
A Review Paper on CMOS, SOI and FinFET Technology In 1958, the first integrated circuit flip-flop was built using two transistors at Texas Instruments. The chips of today contain more than 1 billion transistors. The memory that could once support an entire company’s accounting system is now what a teenager carries in his smartphone. This scale of growth has resulted from a continuous scaling of transistors and other improvements in the Silicon manufacturing process. |
|
 |
3 | 5 |
Why using Single Root I/O Virtualization (SR-IOV) can help improve I/O performance and Reduce Costs In this paper, we will explore why designing systems that have been natively built on SR-IOV-enabled hardware may be the most cost-effective way to improve I/O performance and how to easily implement SR-IOV in PCIe devices. |
| 4 | 4 |
Design Rule Checks (DRC) - A Practical View for 28nm Technology The main objective of this paper is to explain the various types of design rule checks (DRC) violation, their causes and how to fix the various design rule checks (DRC) at lower technology node on block level as well as full chip level implementation while meeting the design rule with respect to latest technology standards. |
|
|
5 | 7 |
Method for Booting ARM Based Multi-Core SoCs In the boot process various modules/peripherals (like clock controller or security handing module and other master/slaves) initialized as per the SoC architecture and customer applications. In Multi core SoCs, first primary core (also called booting core) start up in boot process and then secondary cores are enabled by software. |
 |
6 | 3 |
How to calculate CPU utilization How to calculate CPU utilization |
|
7 | 8 |
PCIe error logging and handling on a typical SoC This paper details first PCIe errors, error logging and then the error handling on a typical SoC. |
|
8 | 6 |
Using SystemVerilog Assertions in RTL Code SystemVerilog Assertions are not difficult to learn; in this tutorial, you will learn the basic syntax, so that you can start using them in your RTL code and testbenches. |
| 9 | 9 |
Design Rule Violation fixing in timing closure Design Rule violation is one of the major challenges being faced by VLSI industry. With ever shrinking technology nodes, and ever increasing gate counts, reaching to more than 40 million on a single die, the complexity of the design is momentous! |
|
| 10 | 10 |
FPGA Implementation of AES Encryption and Decryption This paper presents a high speed, fully pipelined FPGA implementation of AES Encryption and Decryption (acronym for Advance Encryption Standard, also known as Rijndael Algorithm) which has been selected as New Algorithm by the National Institutes of Stand |
|
|
11 | 20 |
Introduction to Low Dropout (LDO) Linear Voltage Regulators Linear voltage regulators are key components in any power-management system that requires a stable and ripple-free power supply. A subset of linear voltage regulators is a class of circuits known as low dropout (LDO) regulators. This paper explains the fundamentals of LDOs and introduces Vidatronic’s LDO technology which solves many of the known shortcomings of LDO circuits. |
|
12 | New!!! |
Understanding - and Reducing - Latency in Video Compression Systems In the video world, latency is the amount of time between the instant a frame is captured and the instant that frame is displayed. Low latency is a design goal for any system where there is real-time interaction with the video content, such as video conferencing or drone piloting. |
| 13 | 13 |
FPGA programming step by step FPGA programming step by step |
|
|
14 | 18 |
Extending 8K over a single, cost-effective wire with TICO lightweight compression With HD omnipresent and 4K seemingly still in its early stages, an even higher resolution, namely 8K (or UHDTV2) is arising. Display and projection manufacturers are already presenting their first 8K-capable products and the 2018 Winter Olympics were partly filmed in this currently largest video resolution format. Taking a peek into the future, Japan’s national TV “NHK” has even announced to broadcast the full Olympic games on home turf in 2020 in glorious 8K. |
|
15 | 11 |
NAND Flash memory in embedded systems This paper presents fundamental information about NAND Flash memory used in Embedded Systems. It discusses various aspects of this storage media such as interface, architecture, error source and error correction as well as software required for building application. |
|
16 | New!!! |
Embedded Software Architecture Specification Developments in Support of SoC Design and Re-use This paper reviews the open literature on general software architecture highlighting techniques applicable to the embedded domain. These areas include use of multiple views, hierarchical patterns, standard modeling, advanced documentation and application of architecture assistance tools. Applying software architecture for embedded re-use is an area identified as not being fully explored in current literature. |
|
17 | 14 |
Encrypting data with the Blowfish algorithm Encrypting data with the Blowfish algorithm |
|
18 | New!!! |
Building Process For the C/C++ Program on Complex SoCs In this paper we have discussed about the typical .c/cpp building flow in complex SoCs.In this paper different stages in C/CPP building flow are mentioned and how the stimulus is generated(corresponding to what is in .c/cpp) to modules and how the core takes the stimulus to module i.e. how core/processors and c/cpp building flow works in typical SoCs. |
|
19 | New!!! |
How to achieve low latency audio/video streaming over IP network? This whitepaper will first define the latency for audio/video transport. It will highlight the usual architecture challenges of an AV over IP transmitter/receiver. A deeper analysis is provided regarding the video compression which is often mistakenly considered as adding too much latency. Eventually, actual latency measurements of the Viper 4K HDMI to IP transmitter/receiver will be presented. |
|
20 | New!!! |
Understanding the Technology behind Traffic Sign Recognition (TSR) Systems A visual-based traffic sign recognition system can be implemented on the automobile with an aim of detecting and recognizing all emerging traffic signs. The same would be displayed to the driver with alarm-triggering features if the driver refuses to follow the traffic signs. |