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20 Most Popular Articles
Updated: Tue, 17 Sep 2019 01:00:02 +0200
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Dynamic Memory Allocation and Fragmentation in C and C++ In C and C++, it can be very convenient to allocate and de-allocate blocks of memory as and when needed. This is certainly standard practice in both languages and almost unavoidable in C++. However, the handling of such dynamic memory can be problematic and inefficient. For desktop applications, where memory is freely available, these difficulties can be ignored. For embedded - generally real time - applications, ignoring the issues is not an option. |
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A Review Paper on CMOS, SOI and FinFET Technology In 1958, the first integrated circuit flip-flop was built using two transistors at Texas Instruments. The chips of today contain more than 1 billion transistors. The memory that could once support an entire company’s accounting system is now what a teenager carries in his smartphone. This scale of growth has resulted from a continuous scaling of transistors and other improvements in the Silicon manufacturing process. |
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Design Rule Checks (DRC) - A Practical View for 28nm Technology The main objective of this paper is to explain the various types of design rule checks (DRC) violation, their causes and how to fix the various design rule checks (DRC) at lower technology node on block level as well as full chip level implementation while meeting the design rule with respect to latest technology standards. |
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Using SystemVerilog Assertions in RTL Code SystemVerilog Assertions are not difficult to learn; in this tutorial, you will learn the basic syntax, so that you can start using them in your RTL code and testbenches. |
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5 | 6 |
Method for Booting ARM Based Multi-Core SoCs In the boot process various modules/peripherals (like clock controller or security handing module and other master/slaves) initialized as per the SoC architecture and customer applications. In Multi core SoCs, first primary core (also called booting core) start up in boot process and then secondary cores are enabled by software. |
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6 | 3 |
PCIe error logging and handling on a typical SoC This paper details first PCIe errors, error logging and then the error handling on a typical SoC. |
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Why using Single Root I/O Virtualization (SR-IOV) can help improve I/O performance and Reduce Costs In this paper, we will explore why designing systems that have been natively built on SR-IOV-enabled hardware may be the most cost-effective way to improve I/O performance and how to easily implement SR-IOV in PCIe devices. |
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8 | 14 |
Scan Lockup Latches - Significant Role in Congestion Lock-up Latches play an important role in fixing timing problems especially for hold timing closure. A lock-up latch is a transparent latch used to avoid large clock skew and mitigate the problem in closing hold timing due to large uncommon clock path. Lock-up latches are used in between the two scan flops having large hold failure probability due to uncommon clock path so that there is no issue in closing timing in a scan chain across domains in scan-shift mode. |
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Understanding - and Reducing - Latency in Video Compression Systems In the video world, latency is the amount of time between the instant a frame is captured and the instant that frame is displayed. Low latency is a design goal for any system where there is real-time interaction with the video content, such as video conferencing or drone piloting. |
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Usage of Multibit Flip-Flop and its Challenges in ASIC Physical Design The continuous need for reduced size of the chip in the VLSI industry brings exciting challenges to the layout engineers for designing better and high-performing integrated circuits, which needs to consume low power even while reducing the silicon area and cost involved. Internal power is a component of the total power consumed by the chip, which is becoming more challenging to handle with the shrinking technology nodes. |
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Introduction to Low Dropout (LDO) Linear Voltage Regulators Linear voltage regulators are key components in any power-management system that requires a stable and ripple-free power supply. A subset of linear voltage regulators is a class of circuits known as low dropout (LDO) regulators. This paper explains the fundamentals of LDOs and introduces Vidatronic’s LDO technology which solves many of the known shortcomings of LDO circuits. |
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12 | 11 |
Encrypting data with the Blowfish algorithm Encrypting data with the Blowfish algorithm |
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13 | 10 |
Multi-Gigabit SerDes: The Cornerstone of High Speed Serial Interconnects by Jerry C. Chen -- Genesys Logic America, Inc. |
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Guide to Choosing the Best DC-to-DC Converter for Your Application This white paper introduces a procedure for choosing the proper DC-DC switching converter for a given application. It explains basic, performance, and optional metrics in detail. It also demonstrates other practical aspects that are sometimes overlooked by system designers. Multiple application examples are provided. |
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Embedded Software Architecture Specification Developments in Support of SoC Design and Re-use This paper reviews the open literature on general software architecture highlighting techniques applicable to the embedded domain. These areas include use of multiple views, hierarchical patterns, standard modeling, advanced documentation and application of architecture assistance tools. Applying software architecture for embedded re-use is an area identified as not being fully explored in current literature. |
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Building Process For the C/C++ Program on Complex SoCs In this paper we have discussed about the typical .c/cpp building flow in complex SoCs.In this paper different stages in C/CPP building flow are mentioned and how the stimulus is generated(corresponding to what is in .c/cpp) to modules and how the core takes the stimulus to module i.e. how core/processors and c/cpp building flow works in typical SoCs. |
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17 | 15 |
System Verilog Assertions Simplified Assertion is a very powerful feature of System Verilog HVL (Hardware Verification Language). Nowadays it is widely adopted and used in most of the design verification projects. This article explains the concurrent assertions syntaxes, simple examples of their usage and details of passing and failing scenarios along with waveform snippets for the ease of understanding. |
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NAND Flash memory in embedded systems This paper presents fundamental information about NAND Flash memory used in Embedded Systems. It discusses various aspects of this storage media such as interface, architecture, error source and error correction as well as software required for building application. |
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Comparing AMBA AHB to AXI Bus using System Modeling This paper discusses the construction of an AMBA Advanced High-performance Bus (AHB) Shared Bus and AMBA Advanced eXtensible Interface (AXI) point-to-point Bus using a graphical modeling environment that achieved approximately 95% cycle accuracy. |
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20 | New!!! |
How to calculate CPU utilization How to calculate CPU utilization |