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20 Most Popular Articles
Updated: Mon, 26 Jun 2017 01:00:01 +0200
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1 | 12 |
Easing the Development of Functionally Safe Controllers This paper identifies the need for increased adoption of functional safety and describes how processors can help address the high level of criticality more simply. It details how the provision of fault detection and control features for random errors can be offered together with protection against systematic software errors, while meeting the demanding high-performance and deterministic execution. |
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Dynamic Memory Allocation and Fragmentation in C and C++ In C and C++, it can be very convenient to allocate and de-allocate blocks of memory as and when needed. This is certainly standard practice in both languages and almost unavoidable in C++. However, the handling of such dynamic memory can be problematic and inefficient. For desktop applications, where memory is freely available, these difficulties can be ignored. For embedded - generally real time - applications, ignoring the issues is not an option. |
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3 | 1 |
How to calculate CPU utilization How to calculate CPU utilization |
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4 | 3 |
Using SystemVerilog Assertions in RTL Code SystemVerilog Assertions are not difficult to learn; in this tutorial, you will learn the basic syntax, so that you can start using them in your RTL code and testbenches. |
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5 | 4 |
PCIe error logging and handling on a typical SoC This paper details first PCIe errors, error logging and then the error handling on a typical SoC. |
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6 | 5 |
Understanding - and Reducing - Latency in Video Compression Systems In the video world, latency is the amount of time between the instant a frame is captured and the instant that frame is displayed. Low latency is a design goal for any system where there is real-time interaction with the video content, such as video conferencing or drone piloting. |
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7 | 8 |
Why using Single Root I/O Virtualization (SR-IOV) can help improve I/O performance and Reduce Costs In this paper, we will explore why designing systems that have been natively built on SR-IOV-enabled hardware may be the most cost-effective way to improve I/O performance and how to easily implement SR-IOV in PCIe devices. |
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8 | 10 |
A Review Paper on CMOS, SOI and FinFET Technology In 1958, the first integrated circuit flip-flop was built using two transistors at Texas Instruments. The chips of today contain more than 1 billion transistors. The memory that could once support an entire company’s accounting system is now what a teenager carries in his smartphone. This scale of growth has resulted from a continuous scaling of transistors and other improvements in the Silicon manufacturing process. |
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9 | 17 |
QEMU based Co-simulation platform - Benefits This paper proposes a flow which illustrates how to develop and test software early in the development phase along with design-verification cycle. Also this paper highlights the benefits of the flow which will not only reduce the development cycle but also improve the quality of product. |
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10 | New!!! |
NAND Flash memory in embedded systems This paper presents fundamental information about NAND Flash memory used in Embedded Systems. It discusses various aspects of this storage media such as interface, architecture, error source and error correction as well as software required for building application. |
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11 | 13 |
FPGA Implementation of AES Encryption and Decryption This paper presents a high speed, fully pipelined FPGA implementation of AES Encryption and Decryption (acronym for Advance Encryption Standard, also known as Rijndael Algorithm) which has been selected as New Algorithm by the National Institutes of Stand |
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12 | 7 |
Multi-Gigabit SerDes: The Cornerstone of High Speed Serial Interconnects by Jerry C. Chen -- Genesys Logic America, Inc. |
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13 | New!!! |
Randsequence: SystemVerilog's unsung hero Constrained random verification, for quite some time now, has been the default verification methodology for complex ASIC/SoC designs. Central to this methodology is the process of letting the randomization engine choose values from a set of possible values. |
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14 | New!!! |
Fronthaul Evolution Toward 5G: Standards and Proof of Concepts This paper will help to navigate through the key concepts of packet based Fronthaul and discuss the implications of the adoption of latest Time-Sensitive-Network (TSN) IEEE 802.1CM standard, the IEEE P1904.3 Radio over Ethernet (RoE) standard and latest Next Generation Fronthaul Interface, (NGFI) IEEE P1914.1 initiatives. Finally, a look at the PoC platforms enabled by Xilinx technology and IP offering from Comcores will be offered. |
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15 | 6 |
Easier UVM Sequences - SystemVerilog UVM Sequence and Task Equivalence SystemVerilog UVM sequences are a powerful way to model stimulus and response for functional verification. Unfortunately using SystemVerilog UVM sequences can require an extensive background in SystemVerilog, the UVM and object oriented programming. This paper explains a collection of techniques to allow the power of sequences with familiarity and simplicity of calling tasks. |
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16 | 14 |
Adaptive Frequency Hopping for Reduced Interference between Bluetooth® and Wireless LAN Adaptive Frequency Hopping for Reduced Interference between Bluetooth® and Wireless LAN |
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17 | 15 |
In-Memory Computing Versus Data Center Networks For data-center architects it seems like a no-brainer. For a wide variety of applications, from the databases behind e-commerce platforms to the big-data tools in search engines to suddenly-fashionable data analytics to scientific codes, the dominant limitation on application response time is storage latency. |
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18 | 11 |
CORTEX-R versus CORTEX-M Cortex-R and cortex-M series is targeted for different requirements and for different applications. It is important to know the parameters and features that separates them as there could be applications where both of them can fit in. This paper is targeted for such a scenario and helps the Designers for selection. The final objective is to help the Designers or Developers to have understanding of Architectures of ARM. |
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19 | New!!! |
Method for Booting ARM Based Multi-Core SoCs In the boot process various modules/peripherals (like clock controller or security handing module and other master/slaves) initialized as per the SoC architecture and customer applications. In Multi core SoCs, first primary core (also called booting core) start up in boot process and then secondary cores are enabled by software. |
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20 | New!!! |
A Phyton Based SoC Validation and Test Environment In this paper, we present an efficient simulation environment we developed, addressing the challenges of both validating and testing a mixed signal RF CMOS transceiver targeting the WLAN market. |
