D&R Industry Articles: Top 20 (Updated Daily)


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20 Most Popular Articles

Updated: Tue, 25 Jun 2019 01:00:01 +0200

Today		Yesterday
	1	New!!!	Choosing a Processor for Machine Learning at the Edge Not all machine learning models need processing on the order of several TOPS. Understanding the performance, latency and accuracy need of your application is a critical first step to choose a processor for machine learning at the edge.
	2	1	Dynamic Memory Allocation and Fragmentation in C and C++ In C and C++, it can be very convenient to allocate and de-allocate blocks of memory as and when needed. This is certainly standard practice in both languages and almost unavoidable in C++. However, the handling of such dynamic memory can be problematic and inefficient. For desktop applications, where memory is freely available, these difficulties can be ignored. For embedded - generally real time - applications, ignoring the issues is not an option.
	3	3	A Review Paper on CMOS, SOI and FinFET Technology In 1958, the first integrated circuit flip-flop was built using two transistors at Texas Instruments. The chips of today contain more than 1 billion transistors. The memory that could once support an entire company’s accounting system is now what a teenager carries in his smartphone. This scale of growth has resulted from a continuous scaling of transistors and other improvements in the Silicon manufacturing process.
	4	2	Using SystemVerilog Assertions in RTL Code SystemVerilog Assertions are not difficult to learn; in this tutorial, you will learn the basic syntax, so that you can start using them in your RTL code and testbenches.
	5	4	Why using Single Root I/O Virtualization (SR-IOV) can help improve I/O performance and Reduce Costs In this paper, we will explore why designing systems that have been natively built on SR-IOV-enabled hardware may be the most cost-effective way to improve I/O performance and how to easily implement SR-IOV in PCIe devices.
	6	5	Design Rule Checks (DRC) - A Practical View for 28nm Technology The main objective of this paper is to explain the various types of design rule checks (DRC) violation, their causes and how to fix the various design rule checks (DRC) at lower technology node on block level as well as full chip level implementation while meeting the design rule with respect to latest technology standards.
	7	13	PCIe error logging and handling on a typical SoC This paper details first PCIe errors, error logging and then the error handling on a typical SoC.
	8	14	Method for Booting ARM Based Multi-Core SoCs In the boot process various modules/peripherals (like clock controller or security handing module and other master/slaves) initialized as per the SoC architecture and customer applications. In Multi core SoCs, first primary core (also called booting core) start up in boot process and then secondary cores are enabled by software.
	9	9	Understanding - and Reducing - Latency in Video Compression Systems In the video world, latency is the amount of time between the instant a frame is captured and the instant that frame is displayed. Low latency is a design goal for any system where there is real-time interaction with the video content, such as video conferencing or drone piloting.
	10	8	Comparing AMBA AHB to AXI Bus using System Modeling This paper discusses the construction of an AMBA Advanced High-performance Bus (AHB) Shared Bus and AMBA Advanced eXtensible Interface (AXI) point-to-point Bus using a graphical modeling environment that achieved approximately 95% cycle accuracy.
	11	6	Introduction to Low Dropout (LDO) Linear Voltage Regulators Linear voltage regulators are key components in any power-management system that requires a stable and ripple-free power supply. A subset of linear voltage regulators is a class of circuits known as low dropout (LDO) regulators. This paper explains the fundamentals of LDOs and introduces Vidatronic’s LDO technology which solves many of the known shortcomings of LDO circuits.
	12	10	Multi-Gigabit SerDes: The Cornerstone of High Speed Serial Interconnects by Jerry C. Chen -- Genesys Logic America, Inc.
	13	12	Scan Lockup Latches - Significant Role in Congestion Lock-up Latches play an important role in fixing timing problems especially for hold timing closure. A lock-up latch is a transparent latch used to avoid large clock skew and mitigate the problem in closing hold timing due to large uncommon clock path. Lock-up latches are used in between the two scan flops having large hold failure probability due to uncommon clock path so that there is no issue in closing timing in a scan chain across domains in scan-shift mode.
	14	20	System Verilog Assertions Simplified Assertion is a very powerful feature of System Verilog HVL (Hardware Verification Language). Nowadays it is widely adopted and used in most of the design verification projects. This article explains the concurrent assertions syntaxes, simple examples of their usage and details of passing and failing scenarios along with waveform snippets for the ease of understanding.
	15	New!!!	Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product This paper explains the changes in the role of the semiconductor industry in the automotive supply chain and seeks to enhance the reader’s knowledge regarding all aspects of the ISO 26262 standard. This paper also discusses the standard’s applicability not only to electronic products, but also to the people and processes employed to create them.
	16	19	FPGA Implementation of AES Encryption and Decryption This paper presents a high speed, fully pipelined FPGA implementation of AES Encryption and Decryption (acronym for Advance Encryption Standard, also known as Rijndael Algorithm) which has been selected as New Algorithm by the National Institutes of Stand
	17	New!!!	A comparison of Network-on-Chip and Busses This whitepaper summarizes the limitations of traditional bus-based approaches, introduces the advantages of the generic concept of NoC, and provides specific data about Arteris’ NoC, the first commercial implementation of such architectures
	18	16	Deliver "Smarter" Faster: Design Methodology for AI/ML Processor Design New design tools can develop circuits for AI and machine learning faster than ever. AI/ML is being used to make those same design tools even faster.
	19	15	Design Rule Violation fixing in timing closure Design Rule violation is one of the major challenges being faced by VLSI industry. With ever shrinking technology nodes, and ever increasing gate counts, reaching to more than 40 million on a single die, the complexity of the design is momentous!
	20	7	Intelligent Vt structuring to avoid Temperature Inversion for Performance gain In the modern era, there is a requirement of achieving high frequency targets with lower power consumption. Achieving both the targets simultaneously is very difficult and the situation becomes even more complex while moving down the technology nodes due to various sub-micron effects like Temperature Inversion comes into picture.

20 Most Popular Articles

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