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New Silicon IP
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NoC Generator
- Drag & Drop Graphical User Interface
- Unified configuration tree view
- Intelligent routing path calculation
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UltraFast BCH Decoder
- Throughput of one codeword per clock cycle
- Fully pipelined design
- Design-time configuration of BCH code size and code rate
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Low-power, high-speed 11-bit SAR ADC on TSMC 28nm HPC+
- 11-bit Resolution
- 4 GSPS Sampling Rate
- 132 mW Power Consumption
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GPU based on Arm's 5th Gen architecture
- Deferred vertex shading (DVS)
- Support for larger tiles of up to 64 × 64, compared to 32 × 32 in Immortalis-G715
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LPDDR5X/5/4X PHY on TSMC N4P
- Low latency, small area, low power
- Compatible with JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs up to 8533 Mbps
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ECDSA sign engine
- Optional Side Channel Attacks countermeasures
- Input/Output EC point verification
- Fully synthesizable, synchronous design
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Smallest GPU to support native HDR applications, suitable for wearable devices, smart home hubs, or mainstream set-top boxes
- 10bits RGBA / YUV for HDR experiences
- Advanced image compression technology
- Fully secure GPU virtualisation with HyperLane
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ABX® Automotive Adaptive Body Biasing Generator - GLOBALFOUNDRIES 22FDX
- Integrated adaptive body bias (ABB) control loop
- Charge pumps for N-Well and P-Well voltages, operated from IO supply voltage level
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100 to 1200MHz phase-locked loop
- TSMC CMOS 55 nm
- Output frequency range from 100 MHz to 1200 MHz
- Fully integrated VCO
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32G Multi Rate Very Short Reach SerDes PHY - GlobalFoundries 12LP and 12LPP
- Line rates from 1.25 up to 32Gbps
- PCIe up to Gen5.0
- Ethernet 10G, 25G, 50G, 100G
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MIPI C-PHY TRx (80-2500Msps) / MIPI D-PHY TRx (80-4500Mbps) Combo PHY on Samsung Foundry LN05LPE S00
- Low power consumption, small area
- Supports both overdrive (0.85V) and normal (0.75V) power
- Support for various lane configurations
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CXL 3.0 Premium Controller with AMBA bridge for CXL.io
- Supports all key required features of the CXL 2.0 spcification and full backwards compatibility with CXL 1.0 and 1.1
Top Silicon IP
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1
Deep learning accelerator for edge and end-point inference
- Configurable MACs from 32 to 4096 (INT8)
- Maximum performance 8 TOPS at 1GHz
- Configurable local memory: 16KB to 4MB
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2
Secure DDR5 Controller with Inline Memory Encryption (IME) Security
- Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
- Multiport Arm® AMBA® interface (AXI™4/AXI™3) with managed QoS or single-port host interface to the DDR controller
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3
32G Multi Rate Long Reach SerDes PHY - GlobalFoundries 12LP and 12LPP
- Line rates from 1.25 up to 32Gbps
- PCIe up to Gen5.0
- PIPE interface
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4
CAN FD Light Bus Controller
- CAN Specifications Support
- No broadcast, no error frames, no advertising errors, simple, robust design
- 11-bit identifier restriction for CAN-FD
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MIPI CSI-2 Controller Core V2
- Fully CSI-2 standard compliant
- 64 and 32 bit core widths
- Transmit and Receive versions
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64-bit RISC-V application processor core with 7-stage pipeline
- 64-bit RISC-V core
- Linux capable
- In-order 7-stage pipeline
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PCIe 5.0 PHY on TSMC N6
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
- Lane margining at the receiver
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TSMC based IO & ESD solutions supporting GPIO, I2C,RGMII, SD, LVDS, HDMI & analog/RF across multiple technology nodes
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DDR4 multiPHY in TSMC
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LPDDR4/3/2 DDR4/3/2 ComboPHY
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Dual Channel Digital Capacitive Sensor Interface
- Each channel has an independent trimmable input capacitance range, for flexibility and dynamic range optimization
- Wide operating temperature range: -40 to 125°C
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PCIe 6.0 SerDes PHY
- Complete SerDes subsystem solution with Rambus PCIe 6.0 controller core
- PIPE 6.0-compliant interface for Rambus PCI Express 6.0 Controller
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