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Neoverse N1 CPU

• Revolutionary Compute Performance
• Infrastructure-Specific Features
• Extreme Scalability and Diversity

IMG A-Series AXE Graphics Processor

• Area-optimised, fillrate-focused designs for cost-sensitive devices

ARC HS46FS and HS47DFS Functional Safety Processors

• High-speed, dual-issue, 10-stage pipeline
• Up to 16 MB instruction and data close coupled memory (CCM)
• 4 KB to 64 KB L1 instruction and data cache

Low Drop Out Voltage Regulator 25mA

• 40nm TSMC Logic LP Process, 8 Metals Used with Deep-Nwell
• 2.25V – 3.6V Input Voltage
• 0.9V – 2.8V 3% Output Voltage

Video Codec IP using RAW input­ (CFA)

• Low complexity for ASIC & FPGA
• No external DDR (optional)
• Extreme low latency

Modern Audio DSP, designed for battery operated, high-performance, audio and voice applications

• Quad 16x16 MACs
• Dual 32x32 MACs
• 4-way VLIW

Safety Vision Processor for Automotive ASIL B/D Applications with 4 Vector Processing Units – ARC EV74FS

• ASIL B and D compliant, or hybrid up to ASIL D
• Integrated safety-critical hardware features
• ECC memories

SM4-XTS engine

• Widebus interface
• Key size: 128 bits
• Key scheduling in hardware

MIPI C-PHY CSI-2 TX+ for TSMC 40ULP

• Supports MIPI Specification for C-PHY Version 1.1
• 80 Msps to 2.5 Gsps data rate in high speed mode

Hardware Offload Engine for 1394b AS5643

• AS5643 compliant interface with hardware based STOF offload
• Hardware DMA engines with message label mapped buffers

eSPI Controller

• Compliant with eSPI rev.1.0 specification
• Supports Master and Slave Modes

Elliptic Curve Accelerator

• Operation over any prime field GF(p)
• ECDSA, EdDSA and ECDH functionality
• EC arithmetic operations: addition, doubling and scalar

Die-to-Die PHY IP in TSMC N7

• Offers leading performance, power, and area / beachfront per terabit
• Includes 16 lanes of NRZ and PAM-4 transmitters or receivers

AI based Real Time 8K 60fps Super Resolution IP

• Very optimized for Real Time upscaling
• Flexible 2x/3x/4x upscaling
• Real time upscaling up to 8K 60fps

PCIe 5.0 SerDes PHY

• Complete SerDes subsystem solution with co-validated Expresso 5.0 digital controller core from Northwest Logic, a Rambus company

250Mbps to 16Gbps Multiprotocol SerDes PMA

• Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
• Extremely low jitter suitable for Enterprise SerDes applications

Elliptic Curve Accelerator

• Operation over any prime field GF(p)
• ECDSA, EdDSA and ECDH functionality
• EC arithmetic operations: addition, doubling and scalar

CXL Controller with AMBA Bridge

• Fully supports the CXL 1.0 and 1.1 specifications
• Supports PCI Express 5.0 mode with 32 GT/s and x16 link width

10-bit, 12-bit, 14-bit, Low Speed SAR ADC in TSMC (180nm, 90nm, 65nm, 55nm, 40nm, 28nm, 16nm, 12nm)

UltraLink D2D PHY

• 1Tbps/mm unidirectional bandwidth
• Low power and low latency
• Easy routing and straightforward integration

Deterministic Random Bit Generator (DRBG)

• NIST 800-90A/B/C compliant
• Health test
• AES-CTR based (CTR_DRBG)

JESD207 RFIC IP

• Compliant with JESD207 specification.
• Full JESD207 RFIC functionality.
• Supports half duplex data transfer.

High speed NoC (Network On-Chip) Interconnect IP

• High Performance
• Low Power Consumption
• Smaller Area

12-bit, High Speed SAR ADC in TSMC (28nm, 16nm, 12nm)