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DesignWare SD/eMMC PHY IP in TSMC 12FFC

• Compliant with eMMC 5.1 HS400, SD 3.0 SDR104, DDR50, JESD8-7a (1.2V/1.8V) and JESD8c.01 (3.3V)

12-bit 160MS/s ADC in TSMC 65nm LP

• TSMC 65nm LP
• 1.2V Supply
• 12-bit High-Speed SAR ADC

SD 4.1 UHS-II PHY for TSMC 12nm FF

• Compliant to SD Specifications Part 1 UHS-II Specification Volume 2: PHY* and SD Specifications Part 1 UHS II Specification Volume 1: System and Protocol”

High Accuracy, low-noise sigma delta DAC

• Dynamic range: 117 dB (20 - 20kHz)
• Excellent THD performance: nTHD < -110 dBFS
• Low out-of-band-noise (OOBN): -60 dBFS

OTP IP

• Silicon-proven currently available at 3 major foundries (Silterra, SMIC, Powerchip)

Ultra Low Power Consumption Processor IP for Deep Learning

• Object detection algorithm such as SSD and SegNet etc. Optimized for semantic segmentation algorithm.

Power-on Reset

• iHP SG25H4 SiGe BiCMOS 0.25 um
• 2.5 V supply voltage
• Low current consumption

Capless Low Drop Out 50mA Regulator

• 40nm TSMC Logic LP
• 2.2V – 3.3V Input Voltage
• 0.8V – 3.0V +-3.5% Output Voltage

DesignWare 56G Ethernet PHY IP in 7-nm

• Supports full-duplex 9.9 to 58Gbps data rates in 1, 2, and 4 lanes
• Enables 50G, 100G, 200G, 400G Ethernet interconnects for wired network infrastructure

I2S/Left-Justified/TDM Digital Audio Interface

• I2S/Left-Justified/TDM-A/TDM-B Formats
• Master/Slave Dual Operation

500Gb/s Throughput SerDes

• 2-4X throughput at >50% energy savings vs conventional SerDes
• No interposer required

GP ULP Temperature Sensor in Silterra 0.18um

• 10bit equivalent resolution
• Ultra low power consumption (8μA)

SerDes Long Reach (LR) 8 lane macro

• 112Gbps PHY on TSMC N7
• Optimized form factor for networking applications

56G Ethernet PHY, TSMC 16FF

• Optimized for performance, power and area
• Includes one, two, or four full-duplex PAM-4 transceivers (transmit and receive functions)

USB3.1 Type-C PHY

• Comply with latest USB3.1 specification
• Support all USB connectors, A, B and Type-C

500Gb/s Throughput SerDes

• 2-4X throughput at >50% energy savings vs conventional SerDes
• No interposer required

GDDR6 Controller

• Supports GDDR6 SGRAM
• Supports up to 16 Gbit/s/pin GDDR6 operation

Dual 12-bit 2.0 GS/s ADC in 28nm

• TSMC 28nm HPC+
• High performance at ultra-low power
• On-chip reference and clock phase generation circuitry

Low Power Multiprotocol SerDes PMA

• Very wide CDR range - operates with data rates from 0.6Gbps to 4.0Gbps
• Compatible with JESD204A, JESD204B, OIF-CEI-6G-SR, CPRI, SGMII, XAUI and V-by-One

GDDR6 PHY

• JEDEC JESD250 standard compliant
• Advanced process node: 7nm
• 2 channels @ 16 bits/channel

Deep Learning based Object Detection IP

• High performance
• Low bandwidth requirement
• Low power consumption

LTE-NB-IoT-RF-Transceiver-IP

DMA AXI4-Stream Interface to AXI Memory Map Address Space

• Converts AXI4-Stream Interface to AXI4/AXI3 Memory Map Data & Control Interface

AI-Optimized eFPGA

• Optimized for AI
• Available in any CMOS node