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Compact RISC-V Processor - 32 bit, 3-stage pipeline, 32 registers
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New Silicon IP
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TLS 1.3 Client IP Core
- Optimized Resource Requirements
- Short Session Establishment Time
- Follows RFC 8446
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0.6V/10, 20uA Reference voltage and current source
- TSMC CMOS 55 nm
- Output voltage 0.6 V
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Multi-standards Video Encoder 4K60fps @500MHz
- Frame buffer compression (FBC)
- Low delay encoding
- Configurable IP
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Chacha20-Poly1305 Accelerator
- Host processor offload
- High performance
- Hardware protected keys
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Die-to-Die Controller IP with AXI Interface
- Low Latency controller for die-to-die connectivity
- Supports PAM-4 and NRZ PHY signaling mode in all data rates
- Reduces BER with optional FEC configurations
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12-Bit 900MS/s High Performance Current Steering DAC on TSMC 40nm
- 40nm TSMC LP Process, 7 Metals Used
- 2.5V, and 1.1V Supplies
- 12 Bit DAC resolution
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DVB-GSE Encapsulator and Decapsulator
- Compliant with ETSI TS 102 606-1 V1.2.1 (Annex D, DVB-GSE Lite)
- Support for multi-protocol encapsulation (IPv4, IPv6, MPEG, Ethernet, etc.)
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HDR ISP framework for multi-camera applications
- Complete HDR ISP video processing framework for multi-channel vision and AI systems
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10 mA LDO voltage regulator (output voltage 1.1V/1.2V/1.3V/1.4V)
- TSMC CMOS 55nm
- High precision stabilization voltage
- Wide input voltage range from 2.25V to 3.6V
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MIPI CSI-2 Receiver LVDS/D-PHY Combo in TSMC28HPC+
- Combo PHY for both MIPI D-PHY CSI-2 RX and LVDS
- TSMC 28HPC+
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High Throughput Rate OFDM Baseband PHY Processor
- Custom OFDMA system based on 802.16e standard features.
- Complete Back-end User IF for primitive MAC integration.
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Capacitor-less 101 dB dynamic range ADC with low power mode and ultra low latency capability
- 101 dB dynamic range
- Down to 3us latency
- GlobalFoundries 22FDX
Top Silicon IP
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1
LPDDR5/4x Subsystem IP
- Compliant with JEDEC Standard JESD209-4B and JESD209-5
- Complaint with DFI 5.0 for PHY and Controller interface
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2
ZLIB compatible compression and decompession, with DMA and AXi interface
- 100% ZLIB compatible
- Fixed Huffman encoding
- Subset of LZ77
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3
32-bit Embedded RISC-V Functional Safety Processor
- Designed for Functional Safety
- Efficient Embedded RISC-V Processor
- Powerful Debug Features
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4
64-bit Multiprocessor with Level-2 Cache-Coherence
- 64-bit in-order dual-issue 8-stage pipeline CPU architecture
- Symmetric multiprocessing up to 4 cores
- Level-2 cache and cache coherence support
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5
Third-Generation Valhall-based Graphics Processing Unit (GPU) for Premium Market
- Command Stream Frontend for Advanced Gaming
- Large Cores Provide Highest-Ever Energy Efficiency
- ML Uplift Brings More Advanced Experiences to Mobile
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6
DesignWare 112G Ethernet PHY IP for TSMC N7 Process
- Supports full-duplex 9.9 to 112Gbps data rates, Enabling 100G, 200G, 400G, 800G Ethernet interconnects for wired network infrastructure
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7
Fractional-N Frequency Synthesizer PLL (3nm - 180nm)
- 1MHz up to 1.6GHz input frequency range
- 1MHz up to 3.6GHz output frequency range
- 24 bit fractional resolution
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8
Controller IP for PCIe 6.0, Supporting Root Port, Endpoint, Dual-mode, Switch Port Configurations with Native User Interface
- Dynamically adjustable application layer frequency down to 8Mhz for increased power savings
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9
ARC HS48 quad-core processor with ASIL-B/ASIL-D support for functional safety applications
- High-speed, dual-issue, 10-stage pipeline
- Up to 16 MB instruction and data close coupled memory (CCM)
- 4 KB to 64 KB L1 instruction and data cache
¹ Top Silicon IP Over the Last Two Weeks (Last update: Jun. 20)
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