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ARC VPX5 high-performance, 512-bit VLIW / SIMD DSP IP for high-end computation applications

• Four-way VLIW combining scalar and vector operations
• 512-bit length vector word supported over a variety of SIMD computation engines

100BASE-T1 automotive ethernet PHY

• IEEE Std 802.3bwâ„¢-2015 compliant automotive Ethernet PHY IP
• Fully integrated PHY IP including AFE, PLL, power regulators and ESD protection

Digital I/O LIbrary - TMSC 130nm BCD

• Schmitt triggered input
• pull up/down control modes
• Slew rate controled output

Bluetooth 5.3 dual mode Baseband Controller

• Bluetooth 4.2/5/5.1/5.2/5.3 dual mode compliant
• Support all the features
• Supports all BR, EDR and BLE packet types

2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Transmitter

• Configurable 1 to 4 data lanes.
• Up to 2.5Gbps per lane.
• Support of all CSI2 primary and secondary data formats.

10 to 50 MHz crystal oscillator

• TSMC CMOS 55 nm
• Output frequency 10-50 MHz
• Wide supply voltage range from 2.2 to 3.6V

DDR5/4 PHY IP for GF12LP+

• Supports JEDEC standard DDR5 and DDR4 SDRAMs
• High-performance DDR PHY supporting data rates up to 4800 Mbps

AES Encoder and Decoder

• Encrypts using the AES Rijndael Block Cipher Algorithm
• Employs key sizes of 128, 192, or 256 bits
• Key expansion function

DO-254 certifiable IP solution for TTEthernet end systems

• RTCA DO-254 DAL A certifiable end system core IP
• Fully compliant with IEEE 802.3, ARINC 664 part 7 and SAE AS6802 standards

PDSCH Encoder and PUSCH Decoder

• Complete implementation of the relevant 3GPP standard
• Improved BLER for UCI control data

Spiking Neural Processor

• Neuromorphic processor
• Sub milliwatt power
• Ultra-low power AI processing

PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection

• Fully compliant with PCI Express Base 5.0 electrical specifications
• Compliant with PIPE5.2 (PCIe) specification
• Supports all power-saving modes (P0, P0s, P1, and P2) defined in PIPE4.4.1 spec

Die-to-Die Controller IP with AXI Interface

• Low Latency controller for die-to-die connectivity
• Supports PAM-4 and NRZ PHY signaling mode in all data rates
• Reduces BER with optional FEC configurations

Power-On-Reset TSMC

• Configurable to your specification
• Programmable threshold
• Programmable delay

DSC Decoder

• Compliant with the VESA DSC 1.2a standards
• Perform encoding
• Support MMAP, BP, MPP and ICH

Spiking Neural Processor

• Neuromorphic processor
• Sub milliwatt power
• Ultra-low power AI processing

PCIe 5.0 SerDes PHY

• Complete SerDes subsystem solution with co-validated Expresso 5.0 digital controller core from Northwest Logic, a Rambus company

Dual-issue, 64-bit RISC-V application processor core with 7-stage pipeline

• 64-bit RISC-V core
• Linux capable
• Dual issue

PHY IP for PCIe in TSMC N6

• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization

Memory management unit (MMU) option for ARC HS5x and HS6x Processor IP

• High-speed, 64-bit, dual-issue, 10-stage pipeline
• 64-bit virtual and 52-bit physical address space

IP platform for intelligence gathering chips at the Edge

• High performance IoT solutions for AI at the Edge can now be created up to 30% faster

Fractional-N Frequency Synthesizer PLL (3nm - 180nm)

• 1MHz up to 1.6GHz input frequency range
• 1MHz up to 3.6GHz output frequency range
• 24 bit fractional resolution

DDR4 PHY

10/100/1000 Ethernet PHY

• TSMC CLN90G
• Operating voltage range: 2.25V ~ 3.63V
• Operating junction temperature range: -40℃ ~ 125℃