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Foundry	GLOBALFOUNDRIES HHGrace IBM LFoundry Renesas Samsung SilTerra SMIC Tower TSMC UMC VIS X-FAB

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APEX 20KC APEX 20KE APEX II Arria Arria 10 Arria 10 GT Arria 10 SoC Arria 10 SX Arria GX Arria GX Arria II Arria II GX Arria II GZ Arria V Arria V GT Arria V GX Arria V GZ Arria V SoC Arria V ST Arria V SX Cyclone Cyclone 10 GX Cyclone 10 LP Cyclone II Cyclone III Cyclone III LS Cyclone IV Cyclone IV E Cyclone IV GX Cyclone Series Cyclone V Cyclone V E Cyclone V GT Cyclone V GX Cyclone V SE Cyclone V SoC Cyclone V ST Cyclone V SX eASIC N2X eASIC N2XT eASIC N3X eASIC N3XS HardCopy HardCopy II HardCopy III HardCopy IV E HardCopy IV GX MAX 10 MAX 10 DF MAX II MAX V Stratix Stratix 10 Stratix 10 GX Stratix 10 MX Stratix 10 SX Stratix 10 TX Stratix GX Stratix II Stratix II GX Stratix III Stratix III E Stratix IV Stratix IV E Stratix IV GT Stratix IV GX Stratix V Stratix V E Stratix V GS Stratix V GT Stratix V GX	Artix-7 Artix-7 -2L Kintex UltraScale Kintex UltraScale+ Kintex-7 Kintex-7 -2L Spartan-3 Spartan-3 XA Spartan-3A Spartan-3A DSP Spartan-3A DSP XA Spartan-3A XA Spartan-3AN Spartan-3E Spartan-3E XA Spartan-6 Spartan-6 -1L Spartan-6 HXT Spartan-6 LX Spartan-6 LXT Spartan-6 XA Spartan-6 XC Spartan-7 Spartan-II Spartan-IIE UltraScale UltraScale+ Virtex UltraScale Virtex UltraScale+ Virtex-4 Virtex-4 FX Virtex-4 LX Virtex-4 SX Virtex-4 XA Virtex-5 Virtex-5 FX Virtex-5 FXT Virtex-5 LX Virtex-5 LXT Virtex-5 SX Virtex-5 SXT Virtex-5 TXT Virtex-6 Virtex-6 -1L Virtex-6 CXT Virtex-6 HXT Virtex-6 LX Virtex-6 LXT Virtex-6 SXT Virtex-6 XC Virtex-7 Virtex-7 -2G Virtex-7 -2L Virtex-7 HT Virtex-7 XT Virtex-7T Virtex-E Virtex-II Virtex-II Pro Zynq UltraScale+ MPSoC Zynq-7000	ispClock ispMACH 4000 LatticeEC/ECP LatticeECP2 LatticeECP2M LatticeECP3 LatticeECP5 LatticeSC LatticeSCM LatticeXP LatticeXP2 MachXO MachXO2 MachXO3 Platform Manager Power Manager II

New Silicon IP

• PCIe Gen 6 SerDes IP

  • PCie Gen 5/6 compliant
  • Up to 112G PAM 4 support
  • less than 6 pj/bit typical power consumption
  
   
  
  

• 32G Medium Reach SerDes PHY

  • Supports medium-reach channels up to 25dB insertion loss
  • Industry’s best power, area and latency
  
   
  
  

• DMA AXI4-Stream to/from AXI4 Memory Map

  • 2 Dedicated DMA Channels
  • AXI4 Interfaces
  • Interrupt Controller
  
   
  
  

• Edge AI Accelerator NNE 1.0

  • Minimum efforts in system integration
  • Speed up AI inference performance
  • Super performance for power sensitive application
  
   
  
  

• PHY IP for PCIe 5.0 on Samsung 8LPP

  • Physical Coding Sublayer (PCS) block with PIPE interface
  • Supports PCIe 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
  • Lane margining at the receiver
  
   
  
  

• USB 3.0 PCIe 2.0 SATA 3.0 Combo PHY IP, Silicon Proven in SAMSUNG 8LPP

  • Compatible with PCIE/USB3/SATA base Specification
  • Fully compatible with PIPE3.1 interface specification
  
   
  
  

• 112Gbps XSR SerDes IP for TSMC 7nm FinFET

  • Interoperability
  • Maximize beach front bandwidth
  • Layout flexibility
  
   
  
  

• RDMA RoCE v2 FPGA IP

  • 100Gbps line rate
  • Under 2 usec latency
  • Standard Verbs API support
  
   
  
  

• Image Signal Processing (ISP) RTL IP

  • For IR/Mono/RGB Bayer/RGB-IR/PDAF/HDR/Fish Eye/3A Sensors Image Process to Human/Machine Vision
  
   
  
  

• Hardware Overlay Management Unit for ARC EM cores

  • Lightweight hardware-based memory management unit (MMU) enabling address translation and access permission validation
  • Fully associative Instruction and Data µTLBs
  
   
  
  

• State-Machine-based Root of Trust

  • Side channel attack resistant
  • Technology and node independent
  • Superior cryptographic protection
  
   
  
  

• AI accelerator

  • High power efficiency
  
   
  
  

Top Silicon IP

• 1

  Ultra-low-power RISC-V based GPU Processor

  • RISC V64GC ISA
  • Multicore Array
  • Multithreaded
  
   
  
  
• 2

  NoC Silicon IP for RISC-V based chips supporting the TileLink protocol

  • Easy to integrate the NoC Silicon IP using interface
  • N master and M slave ports based on customer requirement
  • Supports wide range of memory map.
  
   
  
  
• 3

  32G Chip-to-Chip SerDes PHY

  • Industry’s lowest power, area and latency for operation from 1 to 32 Gbps
  
   
  
  

• 4

  USB4 PHY IP in TSMC 7FF for 40 Gbps Performance

  • Supports USB4, USB 3.2, DisplayPort with HDCP 2.3 security, PCI Express, and Thunderbolt 3 connectivity protocols through USB Type-C connectors and cables
  
   
  
  
• 5

  MIPI D-PHY CSI-2 RX+ 1.5Gbps for Automotive Applications

  • Supports MIPI Alliance Specification for D-PHY Version 2.5
  • Consists of 1 Clock lane and 2 Data lanes
  • Embedded, high performance, and highly programmable PLL
  
   
  
  
• 6

  Mobile GPU core with ray tracing

  • 1.3GRay/s Ray tracing performance per core
  • 50% More geometry and compute capability
  • 1.5TFLOPS FP32 performance per core
  
   
  
  

• 7

  H.265/HEVC 422 10bit Encoder for 4K

  • Compliant with ITU-T H.265, ISO/IEC 23008-2
  • Main / Main 12 Profile Level 1 to 6.1
  • Input format: Annex. B
  
   
  
  
• 8

  10mA to 265mA Linear Li-Ion Battery Charger - GlobalFoundries - 0.130um BCD

  • 10mA to 265mA charging current
  • 3.3V to 4.35V termination voltage
  • Power and charging status indicators
  
   
  
  
• 9

  eDP1.4/DP1.4 TX IP PHY

  • eDP/DP v1.4a compliant Physical layer for Tx
  • Consists of two main link channels and one AUX channel
  • Supports 1.62Gbps(RBR) to 8.1Gbps(HBR3) bit rate
  
   
  
  

• 10

  USB 4.0 Gen3X2 and DP1.4 X4 PHY IP with Type-C connector support

  • Worldwide smallest USB4.0 PHY IP in 7nm process.
  • Fully compliant with Universal Serial Bus USB4.0 Gen3/Gen2/Gen1, USB3.2 Gen2/Gen1 and 2.0 electrical specifications.
  
   
  
  
• 11

  Balanced IP core for ChaCha20-Poly1305 AEAD algorithm

  • Moderate resource requirements
  • Performance
  • High Throughput with Short Latency
  
   
  
  
• 12

  Innovative Ultra-High-Speed Chiplet Solution

  • Available in any 40nm or below technology nodes
  • Offers leading performance, power, and area per terabit
  
   
  
  

¹ Top Silicon IP Over the Last Two Weeks (Last update: Dec. 5)

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