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Image Signal Processor

• Gamma correction
• 3A(AWB/AE/AF)
• Black level compensation

NVMe Host Controller

• NVMe host controller with AXI control and data path interfaces
• Supports vendor-specific PCIe hard IP
• Supports PCIe soft IP

PHY IP for PCIe 6.0 in TSMC N5

• Supports the latest features of PCIe 6.0 specification
• Supports PAM-4 signaling and up to x16 lane configurations with bifurcation

Serial Peripheral Interface - Master/Slave with single, dual, quad and octal SPI Bus support

• Operates with 8, 16 and 32 bit CPUs
• Full duplex synchronous serial data transfer
• DMA support

20-Bit 20Hz Sigma Delta ADC for high precision sensor acquisition

• TSMC 180nm
• 2.97V to 3.63V Supplies
• 20-bit sigma-delta (ΣΔ) low power analog-to-digital converter (ADC)

Versatile AES256 IP core (ECB, CBC, CFB, OFB, CTR)

• Moderate resource requirements
• Performance
• Standard Compliance

Comprehensive IP platform for edge to on-device AI

• Scalable Design to Adapt to Various AI Workloads
• Efficient in Mapping State-of-the-Art DL/AI Workloads
• End-to-End Software Toolchain for All Markets and Large Number of Frameworks

24-bit/-140 dB THD+N Multi-Channel Audio Async Sample Rate Converter

• Achieves very low THD+N: average -140dB, maximum -130dB
• 20 ms seconds sync time after reset

MIPI-I3C Master/Slave HDR-DDR compliance with Spec v1.1.1

• Compliance as per MIPI I3C - V.1.1.1 Release .
• Two wire serial interface up to 12.5 MHz using Push-Pull and open drain

HBM2E PHY for TSMC N5

• Complete HBM2/HBM2E IP solution, including PHY, controller and verification IP, reduces integration risk while minimizing time-to-market

AES-XTS, 256-bit key, balanced version

• Moderate resource requirements
• Performance
• Standard Compliance

4 lane 2.5Gbps CSI2-2.1 compliant serial video receiver

• Programmable 1 to 4 lanes, 2.5Gbps per lane
• Pseudo-Random Bit Sequence (PRBS) descrambling
• 16-way deserializer per lane

Bunch of Wires [BoW] PHY

• Emerging Standard Knowledge
• Flexibly Configurable
• Best in Class PPA

RISC-V 32bit CPU which supports ISO26262 ASIL D

• RISC-V 32bit General Purpose Tiny Core
• ISO26262:2018 ASIL D compliant SEooC IP
• RISC-V Solution by Collaborating with Partners

eTCAM (Embedded Ternary Content Addressable Memory IP

• One cycle operation latency (without priority encoder)
• Valid Bit per entry to reduce power
• Valid Bit reset in one cycle support

Nano power DC-DC converter in TSMC 22ULL

• Ultra-low quiescent current to ensure minimum current consumption in deep sleep / hibernation mode
• High efficiency at light load to extend battery lifetime

eDP1.4/DP1.4 TX IP PHY

• eDP/DP v1.4a compliant Physical layer for Tx
• Consists of two main link channels and one AUX channel
• Supports 1.62Gbps(RBR) to 8.1Gbps(HBR3) bit rate

DDR4/LPDDR4/LPDDR4X PHY

• Multi-interface support. LPDDR4 up to 3200Mbps and DDR4/LPDDR4X up to 4267Mpbs.
• Support LPDDR4X 0.6V VDDQ.

1x64 Bits OTP (One-Time Programmable) IP, GlobalFoundries 22nm FDX 0.8V/1.8V

• Fully compatible with GlobalFoundries 22nmFDX 0.8V/1.8V
• Read voltage: 0.8V+/-10% VDD and 0.8V or 1.8V VDDP.

Quad core IP platform with integrated Arm security subsystem

• Single channel, video & data processing

RISC-V processor with vector extension certified for ISO 26262 ASIL D ready

• Off-loading heavy calculations from microcontrollers
• MIMD-based embedded vector processor
• Certificated standards for automotive functional safety, ISO26262 ASIL D Ready

High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for TSMC (65nm, 40nm, 28nm, 16nm)

Multiple Pixel Processing Camera Image Signal Processing Core

• Support RGB Bayer progressive image sensor and Monochrome progressive image sensor
• Support 8 ~ 14 bit input data Bayer

PCI Express - Configurable PCI Express 4.0 IP

• Compliant with "PCI Expressâ„¢ Base Specification, Rev. 4.0 Version 1.0"
• Compliant with "PHY Interface For the PCI Express, SATA, and USB3.1 Architectures"