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Foundry	GLOBALFOUNDRIES HHGrace IBM LFoundry Renesas Samsung SilTerra SMIC Tower TSMC UMC X-FAB

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APEX 20KC APEX 20KE APEX II Arria 10 Arria GX Arria II GX Arria II GZ Arria V GT Arria V GX Arria V GZ Arria V ST Arria V SX Cyclone Cyclone II Cyclone III Cyclone III LS Cyclone IV GX Cyclone V GT Cyclone V GX Cyclone V SE Cyclone V ST Cyclone V SX HardCopy HardCopy II HardCopy III HardCopy IV E HardCopy IV GX MAX II MAX V Stratix Stratix 10 Stratix GX Stratix II Stratix II GX Stratix III Stratix III E Stratix IV Stratix IV GT Stratix IV GX Stratix V E Stratix V GS Stratix V GT Stratix V GX	Artix-7 Artix-7 -2L Kintex UltraScale Kintex UltraScale+ Kintex-7 Kintex-7 -2L Spartan-3 Spartan-3 XA Spartan-3A Spartan-3A DSP Spartan-3A DSP XA Spartan-3A XA Spartan-3AN Spartan-3E Spartan-3E XA Spartan-6 Spartan-6 -1L Spartan-6 HXT Spartan-6 LX Spartan-6 LXT Spartan-6 XA Spartan-6 XC Spartan-7 Spartan-II Spartan-IIE UltraScale UltraScale+ Virtex UltraScale Virtex UltraScale+ Virtex-4 Virtex-4 FX Virtex-4 LX Virtex-4 SX Virtex-4 XA Virtex-5 Virtex-5 FX Virtex-5 FXT Virtex-5 LX Virtex-5 LXT Virtex-5 SX Virtex-5 SXT Virtex-5 TXT Virtex-6 Virtex-6 -1L Virtex-6 CXT Virtex-6 HXT Virtex-6 LX Virtex-6 LXT Virtex-6 SXT Virtex-6 XC Virtex-7 Virtex-7 -2G Virtex-7 -2L Virtex-7 HT Virtex-7 XT Virtex-7T Virtex-E Virtex-II Virtex-II Pro Zynq UltraScale+ MPSoC Zynq-7000	ispClock ispMACH 4000 LatticeEC/ECP LatticeECP2 LatticeECP2M LatticeECP3 LatticeSC LatticeSCM LatticeXP LatticeXP2 MachXO MachXO2 MachXO3 Platform Manager Power Manager II

New Silicon IP

• CryptoManager RISC-V Root of Trust Programmable Secure Processing Core

  • Hardware root of trust featuring a custom 32-bit RISC-V processor
  • Secure in-core processing and industry-leading anti-tamper
  
   
  
  

• Video over IP IP cores

  • Support for up to 256 channels of video, audio and meta-data
  • Protocols can be configured on a per-channel basis (mix Sony, ASPEN, ST2110, ST2022-6)
  
   
  
  

• Low noise 12-bit voltage DAC

  • 180nm TSMC Logic Process12bit resolution
  • 1.8V & 3.3V Supply Voltage
  
   
  
  

• Serial Front Panel Data Port Gen3

  • VITA 17.3-2018 Compliant
  • Multi-lane channel bonding support
  • 64B/67B Framing Layer
  
   
  
  

• PCI Express 4.0 PHY TSMC 16FFC

  • Designed to the PCIe 4.0, 3.1, 2.1 and 1.1 specifications as well as the PHY interface for PCIe (PIPE) 4.3 specifications
  
   
  
  

• 2.8 Gbps LVDS IO

  • Different bump options for optimum usage of I/O ring
  • Power down feature for saving power
  
   
  
  

• XS800 100G OTN Transponder

  • Implements 16-bit register interface for programming of internal registers.
  • Complies with IEEE 802.3ba, ITU-T G.709 and ITU-T G.798 specifications.
  
   
  
  

• IEEE 802.11ah MAC/PHY

  • 1 MHz and 2 MHz channel width
  • S1G_1M, S1G_SHORT PPDU
  • Mandatory MAC including TXOP, RID, SST, TWT, AID,…, RAW
  
   
  
  

• DesignWare DDR4/3 PHY IP in TSMC 12FFC Process

  • Supports JEDEC standard DDR4, DDR3, and DDR3L SDRAMs
  • High-performance DDR PHY supporting data rates up to 3200 Mbps
  
   
  
  

• 16-Bit, 16kSPS SD ADC

  • 55nm 2P7M SMIC CMOS technology
  • Programmable Gain : 0 to 50dB
  • Selectable Microphone bias : -1.3V/2.5V 2.9V
  
   
  
  

• 400Gb/s Ethernet Mapper with RMON

  • Suitable for FPGA and/or ASIC implementations.
  • Available under flexible single use licensing terms
  • Integration support and maintenance available.
  
   
  
  

• MACsec Engine

  • Can aggregate several 10, 40 or 100 GBE link
  • Throughput from 10 Gbps up to 800 Gbps
  • Scalability enabling trade-off between throughput, area and latency
  
   
  
  

Top Silicon IP

• 1

  Deep Learning Processor

  • Unified deep learning/vision/video architecture enables flexibility
  • Low power extends battery life and prevents overheating
  • Single scalable architecture
  
   
  
  
• 2

  Bus encryption IP core

  • On-the-fly decryption
  • In-place execution of encrypted code
  • Decryption based on AES fully compliant with NIST FIPS 197
  
   
  
  
• 3

  Multi-Protocol 16G PHY IP in TSMC 12FFC

  • Operating from 1.23 to 16 Gbps 1 data-rate;
  • PCI Express (PCIe) 4.0/3.1/2 .1/1.1, 1 with lane margining
  
   
  
  

• 4

  SHA-256 Cryptocurrency Mining Accelerator IP Platform

  • High Performance SHA-256 multi hash pipelines for Cryptocurrency Mining (eg Bitcoin and derivatives)
  
   
  
  
• 5

  High speed Network On-Chip Interconnect IP

  • High Performance
  • Low Power Consumption
  • Smaller Area
  
   
  
  
• 6

  12-Bit SAR ADC in GlobalFoundries 22nm FDSOI

  • Process: GF22n FDSOI 0.8V, metal stack is 7L1X_1T6X_LB
  • Resolution: 12-bit resolution
  • DNL: +/-1.5 LSB, INL: +/-3 LSB
  
   
  
  

• 7

  MACsec Engine

  • Can aggregate several 10, 40 or 100 GBE link
  • Throughput from 10 Gbps up to 800 Gbps
  • Scalability enabling trade-off between throughput, area and latency
  
   
  
  
• 8

  High Performance DDR3/4/LPDDR3/4 Memory Controller

  • JEDEC compliant LPDDR3/4, DDR3/4 support
  • Up to 4 ranks / channel (configurable)
  
   
  
  
• 9

  Blake2b Cryptocurrency Mining Accelerator IP Platform

  • High Performance Blake2b multi hash pipelines for Cryptocurrency Mining
  • Multiple Concurrent Pipelines
  
   
  
  

• 10

  400Gb/s Ethernet Mapper with RMON

  • Suitable for FPGA and/or ASIC implementations.
  • Available under flexible single use licensing terms
  • Integration support and maintenance available.
  
   
  
  
• 11

  SCRYPT Cryptocurrency Mining Accelerator

  • High Performance Scrypt multi hash pipelines for Cryptocurrency Mining
  • Multiple Concurrent Pipelines
  
   
  
  
• 12

  IEEE 802.11ah MAC/PHY

  • 1 MHz and 2 MHz channel width
  • S1G_1M, S1G_SHORT PPDU
  • Mandatory MAC including TXOP, RID, SST, TWT, AID,…, RAW
  
   
  
  

¹ Top Silicon IP Over the Last Two Weeks (Last update: Apr. 15)

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