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GDDR6 PHY

• Low Risk
• Proven
• High Bandwidth Solution

25GbE TCP Offloading Engine

• TCP/IP off-loading engine for 10/25GBASE-R
• Support IPv4 protocol
• Support one port connection

64-bit CPU with RISC-V Vector Extension

• AndeStarâ„¢ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
• RISC-V vector extension

Prodigy IoT/Edge Licensable Hardware IP

• TPU AI/ML Inference IP Architecture

High performance Linux-capable processor

• Fully-compliant with the RISC-V ISA specification
• RV64GC U84 Application Core
• Integrated 128KB L2- Cache with ECC

DesignWare LPDDR5/4/4X Controller IP with advanced features package

• Complete, integrated LPDDR5/4/4X solution from a single vendor
• Supports LPDDR5, LPDDR4, and LPDDR4X protocols

12-Bit 40MS/s Current Steering DAC

• TSMC 65nm Logic LP Process
• 3.3V and 1.2V Supplies
• Single VDAC

Xtra-Long-Reach (XLR) Multi-Standard-Serdes (MSS)

• Most Likely Sequence Detector(MLSD)
• High speed A/D
• Sub-sampling clock multiplier

8 bit SAR ADC

• 8 bits resolution.
• Supply voltage 1.6-2.0V.
• 7.3 bit ENOB.

Process/Voltage/Temperature Detector

• Temperature measurement range -40°C ÷ +125°C
• Core and IO Voltage measurement range: 0.65V÷1.15V and 2.0V÷3.6V
• High accuracy temperature and voltage measurements

Ultra-Low-Power Temperature/Voltage Monitor in 16nm CMOS

• Class leading performance
• Ultra low power
• Compact area

MIPI D-PHY, CSI-2 TX+ for TSMC40ULP

• Supports MIPI Alliance Specification for D-PHY Version 2.1
• Consists of 1 Clock lane and 4 Data lanes

Linux capable 64-bit RISC-V processor core with 7-stage pipeline

• 64-bit RISC-V core
• Linux capable
• In-order 7-stage pipeline

HEVC + AVC Multi-Encoder IP for 4K@60fps

• Capable of encoding HEVC (3840x2160) @60fps 500MHz.
• Parallel tools
• High performance offline CABAC encoding

Small-size ISP (Image Signal Processing) IP ideal for AI camera systems.

• High performance
• Function expansion support

32G Multi Rate SerDes PHY - GlobalFoundries 22FDX

• Line rates from 1.25 up to 32Gbps
• PCIe up to Gen4.0
• PIPE interface

LPDDR5/4/4X Controller for Automotive

• Supports JEDEC standard LPDDR5, LPDDR4, and LPDDR4X SDRAMs
• Multiport Arm® AMBA® interface (4 AXIâ„¢/3 AXIâ„¢) with managed QoS or single-port host interface to the DDR controller

Fast floating point option for the ARC HS4x and HS4xD processors

• IEEE 754 compliant
• Support for half-precision, singleprecision, or double-precision operation

Fractional-N Frequency Synthesizer PLL (5nm - 180nm)

• 1MHz up to 1.6GHz input frequency range
• 1MHz up to 3.6GHz output frequency range
• 24 bit fractional resolution

Multi-rate/Multi-lane 1.6T Ethernet Package

• PCS layer formed by bonded 2x 400GE PCS in PCS Layer
• Using 32 virtual logical lanes based on 2 x 400GE PCS to reduce power in 800G operation

AV1 fixed function HW decoder IP for 4Kp60 4:2:0 10 bit

• Capable of decoding AV1 MAIN profile @L5.1 Main-tier 50Mbps
• Input; 8 or 10 bit, 420 samplings only
• Max Display Resolution: 8192x8192

10-bit SAR ADC TSMC

• Sampling Rate options: 1 MSps;2 MSps;5 MSps;10 MSps;15 MSps;20 MSps
• Quick re-configuration to your specification
• Up to 10-bit resolution

NVM OTP in TSMC (180nm, 130nm, 110nm, 90nm, 65nm, 55nm, 40nm, 28nm, 16nm, 12nm)

TSMC CLN7FF 7nm Clock Generator PLL

• 800MHz-4000MHz
• Delivers optimal jitter performance over all multiplication settings.