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8~13M pixel sensor support High Quality ISP IP

• Image: Up to 13MPixel
• Video: Up to 13MPixel at 60 FPS
• Input formats: Bayer (8bit, 10bit, 12bit), YUV(16bit)

Gen-Z 1.0 Controller

• Gen-Z specification 1.0a compliant
• Gen-Z PHY specification 0.9a compliant
• Explicit and P2P Classes support

Zero Additional Mask MTP IP, 2.2-5V 4kbit HHGrace 180BCD

• High Temperature Operation
• Large Program Size enables Short Testing Time
• Low Cost

Single port 10/100 Fast Ethernet Transceiver

• TSMC12nm FFC
• IEEE 802.3u auto-negotiation, supporting 100Base-TX and 10BASE-T networks over twisted-pair cable in full-duplex or half-duplex mode

12-bit Temperature Sensor

• TSMC 40nm LP (Low Power Process)
• No Analog Options
• 1.1V Core & 2.5V I/O Supplies

Multi-Protocol 25G PHY in TSMC 16FF

• Supports 1.25 to 25.8 Gbps data-rate
• Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols

SD 3.0 I/O Pad Set

• TSMC 16nm

MIPI CSI-2 Tansmitter v 2.1, C-PHY compatible

• Fully compliant to MIPI standard
• Small footprint
• Code validated with Spyglass

DVB-GSE IPv4/IPv6 Encapsulator

• GSE fragmentation & encapsulation of IPv4/IPv6 packets
• Designed for high throughput1 and low latency

Integrated Fractional-N RF Synthesizer

• TSMC 0.18 µm RF CMOS process
• 3V and 1.8V Power Supply
• VCO phase noise -116 dBc/Hz at 1MHz offset

HDMI 2.1 RX PHY IP for TSMC 16FFC

• HDMI 2.1 RX IP solution includes PHYs, controllers, verification IP
• Compliant with the HDMI 2.1, 2.0, 1.4 and HDCP 2.2, 1.4 specifications

V-by-One PCS Tx IP Core

• Fully compatible with the V-by-One HS 1.4 standard release

Deep neural-network accelerator (DNA) AI processor

• Specialized design to take advantage of sparsity in weights and activations for compute and bandwidth reduction

RISC-V SOC Platform

• Configurable number of processor cores
• Configurable L1/L2 Cache size

CNN Compact Accelerator

• Support convolution layer, max pooling layer, batch normalization layer and full connect layer
• Configurable bit width of weight (16 bit, 1 bit)

First High Performance Split-Lock DynamIQ CPU

• Flexibility with Split-Lock
• Thermal Efficiency
• Superscalar Processor Core

25Gbps Multi-Link and Multi-Protocol PHY for TSMC 7nm FinFET

• Maturity – Silicon proven and robust Serdes architecture
• Flexibility – Maximum flexibility and reconfigurability
• Ease-of-use – Faster to integrate, bring-up, and support

Compact High-Speed 32-bit CPU for Real-time and Linux Applications

• AndeStar V5 ISA, compliant to RISC-V
• Floating point extensions
• Andes extensions

Multi-Protocol 25G PHY IP for TSMC 7FF

• Supports 1.25 to 25.8 Gbps data-rate
• Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols

7 way DDR combo

• Full DDR4 capability
• Full DDR3 / DDR3L / DDR3U capability
• Full LPDDR4 capability

DVB-GSE Ethernet Tunnel IP Core

• GSE encapsulation of Ethernet frames
• Designed for high throughput and low latency

12-bit 285kS/s SAR ADC w/ Temp. Sensor

• TSMC 0.18um eLL process
• 1.8V and 3.0V Supply
• 12-bit SAR ADC

CAN FD Bus Controller

AES high-speed and multi-purpose crypto engine (ECB, CTR, CBC, CFB, OFB, XTR, CCM, GCM, OMAC)