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Digital Fractional-N PLL for 5G Applications

• Fractional-N digital PLL architecture, using an LC-tank oscillator

12 Bit 17 kS/s Cyclic ADC

• Resolution: 12 bit
• Conversion rate: up to 17 kS/s
• Power consumption: 50 μW @ 2.4 V

PowerVR Series9XMP Graphic Processor

• Augmented & Virtual reality
• Automotive (ADAS)
• Smartphone & tablet

Low Power TCAM depth 1K and width upto 280

• Lowest Power TCAM
• One of the fastest TCAM
• Robust design

Neural network-based speech recognition technology for voice assistants and IoT devices

• WhisPro is optimized for always listening devices, enabled by a wake-up trigger phrase.

GDDR6 PHY

• World’s first silicon proven commercial GDDR6 IP
• Advanced process node: GF14 LPP/ SAMSUNG 14LPP
• JEDEC JESD250 standard compliant

High performance vector floating point unit option for EV6x Embedded Vision Processor

• Optimized for high frame-rate and video resolution embedded vision applications

Digital Oscillator in TSMC 55nm ULP eFlash

• 55nm TSMC ULP eFlash , 6 Metals Used with Deep-Nwell
• 2.5V and 1.2V Supply
• Operating Frequency Range: 85 115MHz

Single Port, Ultra Low Power, Low Voltage, GF 22FDX, Single Port Compiler

• 0.65V and 0.5V Logic Support
• Integrated Power Solutions
• Output Isolation

400MHz, 12-bit Continuous time Delta Sigma ADC

• 60dB SNDR
• Continuous-time ΔΣ ADC
• High clock jitter tolerance

Multipurpose Hybrid DSP and Controller Architecture Family

• Parallel processing SIMD Instruction Set Architecture
• 5-way VLIW micro-architecture
• Single or dual scalar compute engines

Current Sink Output Amplifier - TSMC 55nm eFlash ULP

• 55nm TSMC eFlash ULP Process, 7 Metals Used
• (No Analog Options)
• 2.5V and 1.2V Supplies

Deep Learning Processor

• Unified deep learning/vision/video architecture enables flexibility
• Low power extends battery life and prevents overheating
• Single scalable architecture

Deep neural-network accelerator (DNA) AI processor

• Specialized design to take advantage of sparsity in weights and activations for compute and bandwidth reduction

RISC-V SOC Platform

• Configurable number of processor cores
• Configurable L1/L2 Cache size

SerDes Long Reach (LR) 8 lane macro

• 112Gbps PHY on TSMC N7
• Optimized form factor for networking applications

AI Processor for Deep Learning at the Edge

• Self-contained AI Processor
• Offers a considerable step-up in performance.

Deep Learning based Object Detection IP

• High performance
• Low bandwidth requirement
• Low power consumption

500Gb/s Throughput SerDes

• 2-4X throughput at >50% energy savings vs conventional SerDes
• No interposer required

MIPI C-PHY and D-PHY Combo

• Dual mode PHY can support C-PHY and D-PHY
• Supports MIPI Specification for D-PHY Version 1.2
• Supports MIPI Specification for C-PHY Version 1.0

CAN Bus Controller with Message Filter (Mailbox concept)

12-bit, 1200 MSPS Ultra Low Power ADC in 28nm CMOS

Fractional-N Frequency Synthesizer PLL (5nm - 180nm)

• 1MHz up to 1.6GHz input frequency range
• 1MHz up to 3.6GHz output frequency range
• 24 bit fractional resolution

Camera SLVS-EC/sub-LVDS combo Receiver 2.5Gbps 8/12-Lane

• SLVS-EC / MIPI CSI compliant