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Process Node	7nm 8nm 10nm 12nm 16nm 20nm 22nm 28nm 40nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm
Foundry	GLOBALFOUNDRIES HHGrace IBM LFoundry Renesas Samsung SilTerra SMIC Tower TSMC UMC X-FAB

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APEX 20KC APEX 20KE APEX II Arria 10 Arria GX Arria II GX Arria II GZ Arria V GT Arria V GX Arria V GZ Arria V ST Arria V SX Cyclone Cyclone II Cyclone III Cyclone III LS Cyclone IV GX Cyclone V GT Cyclone V GX Cyclone V SE Cyclone V ST Cyclone V SX HardCopy HardCopy II HardCopy III HardCopy IV E HardCopy IV GX MAX 10 MAX II MAX V Stratix Stratix 10 Stratix GX Stratix II Stratix II GX Stratix III Stratix III E Stratix IV Stratix IV GT Stratix IV GX Stratix V E Stratix V GS Stratix V GT Stratix V GX	Artix-7 Artix-7 -2L Kintex UltraScale Kintex UltraScale+ Kintex-7 Kintex-7 -2L Spartan-3 Spartan-3 XA Spartan-3A Spartan-3A DSP Spartan-3A DSP XA Spartan-3A XA Spartan-3AN Spartan-3E Spartan-3E XA Spartan-6 Spartan-6 -1L Spartan-6 HXT Spartan-6 LX Spartan-6 LXT Spartan-6 XA Spartan-6 XC Spartan-7 Spartan-II Spartan-IIE UltraScale UltraScale+ Virtex UltraScale Virtex UltraScale+ Virtex-4 Virtex-4 FX Virtex-4 LX Virtex-4 SX Virtex-4 XA Virtex-5 Virtex-5 FX Virtex-5 FXT Virtex-5 LX Virtex-5 LXT Virtex-5 SX Virtex-5 SXT Virtex-5 TXT Virtex-6 Virtex-6 -1L Virtex-6 CXT Virtex-6 HXT Virtex-6 LX Virtex-6 LXT Virtex-6 SXT Virtex-6 XC Virtex-7 Virtex-7 -2G Virtex-7 -2L Virtex-7 HT Virtex-7 XT Virtex-7T Virtex-E Virtex-II Virtex-II Pro Zynq UltraScale+ MPSoC Zynq-7000	ispClock ispMACH 4000 LatticeEC/ECP LatticeECP2 LatticeECP2M LatticeECP3 LatticeSC LatticeSCM LatticeXP LatticeXP2 MachXO MachXO2 MachXO3 Platform Manager Power Manager II

New Silicon IP

• Low-power 32-bit RISC-V processor

  • RISC-V RV32 instruction set:
  • Machine mode only
  • 32 vectorized interrupts
  
   
  
  

• CAN-FD controller compatible with both CAN 2.0B and CAN-FD

  • Compatible with both CAN 2.0B and CAN-FD
  • Fully compliant with ISO 11898-1:2015
  
   
  
  

• 12-bit 4MS/s ADC

  • TSMC 22nm ULL Process
  • No Analog Options
  • 0.8V Core Supply
  
   
  
  

• 12-bit High Speed SAR IQ-ADC

  • 320MSPS, 0.8V
  • TSMC12FFC
  
   
  
  

• 8~13M pixel sensor support High Quality ISP IP

  • Image: Up to 13MPixel
  • Video: Up to 13MPixel at 60 FPS
  • Input formats: Bayer (8bit, 10bit, 12bit), YUV(16bit)
  
   
  
  

• Gen-Z 1.0 Controller

  • Gen-Z specification 1.0a compliant
  • Gen-Z PHY specification 0.9a compliant
  • Explicit and P2P Classes support
  
   
  
  

• Zero Additional Mask MTP IP, 2.2-5V 4kbit HHGrace 180BCD

  • High Temperature Operation
  • Large Program Size enables Short Testing Time
  • Low Cost
  
   
  
  

• Single port 10/100 Fast Ethernet Transceiver

  • TSMC12nm FFC
  • IEEE 802.3u auto-negotiation, supporting 100Base-TX and 10BASE-T networks over twisted-pair cable in full-duplex or half-duplex mode
  
   
  
  

• 12-bit Temperature Sensor

  • TSMC 40nm LP (Low Power Process)
  • No Analog Options
  • 1.1V Core & 2.5V I/O Supplies
  
   
  
  

• Multi-Protocol 25G PHY in TSMC 16FF

  • Supports 1.25 to 25.8 Gbps data-rate
  • Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
  
   
  
  

• SD 3.0 I/O Pad Set

  • TSMC 16nm
  
   
  
  

• MIPI CSI-2 Tansmitter v 2.1, C-PHY compatible

  • Fully compliant to MIPI standard
  • Small footprint
  • Code validated with Spyglass
  
   
  
  

Top Silicon IP

• 1

  Deep neural-network accelerator (DNA) AI processor

  • Specialized design to take advantage of sparsity in weights and activations for compute and bandwidth reduction
  
   
  
  
• 2

  RISC-V SOC Platform

  • Configurable number of processor cores
  • Configurable L1/L2 Cache size
  
   
  
  
• 3

  CNN Compact Accelerator

  • Support convolution layer, max pooling layer, batch normalization layer and full connect layer
  • Configurable bit width of weight (16 bit, 1 bit)
  
   
  
  

• 4

  First High Performance Split-Lock DynamIQ CPU

  • Flexibility with Split-Lock
  • Thermal Efficiency
  • Superscalar Processor Core
  
   
  
  
• 5

  Multi-Protocol 25G PHY IP for TSMC 7FF

  • Supports 1.25 to 25.8 Gbps data-rate
  • Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
  
   
  
  
• 6

  25Gbps Multi-Link and Multi-Protocol PHY for TSMC 7nm FinFET

  • Maturity – Silicon proven and robust Serdes architecture
  • Flexibility – Maximum flexibility and reconfigurability
  • Ease-of-use – Faster to integrate, bring-up, and support
  
   
  
  

• 7

  Compact High-Speed 32-bit CPU for Real-time and Linux Applications

  • AndeStar V5 ISA, compliant to RISC-V
  • Floating point extensions
  • Andes extensions
  
   
  
  
• 8

  DVB-GSE Ethernet Tunnel IP Core

  • GSE encapsulation of Ethernet frames
  • Designed for high throughput and low latency
  
   
  
  
• 9

  Integrated Fractional-N RF Synthesizer

  • TSMC 0.18 µm RF CMOS process
  • 3V and 1.8V Power Supply
  • VCO phase noise -116 dBc/Hz at 1MHz offset
  
   
  
  

• 10

  RISC-V Processor - 32 bit, 3-stage

  • Support for RV32IM
  • 3-stage pipeline
  • 32 or 64bit general purpose registers
  
   
  
  
• 11

  HDMI 2.1 RX PHY IP for TSMC 16FFC

  • HDMI 2.1 RX IP solution includes PHYs, controllers, verification IP
  • Compliant with the HDMI 2.1, 2.0, 1.4 and HDCP 2.2, 1.4 specifications
  
   
  
  
• 12

  V-by-One PCS Tx IP Core

  • Fully compatible with the V-by-One HS 1.4 standard release
  
   
  
  

¹ Top Silicon IP Over the Last Two Weeks (Last update: Oct. 21)

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