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HBM2E PHY for TSMC N5

• Complete HBM2/HBM2E IP solution, including PHY, controller and verification IP, reduces integration risk while minimizing time-to-market

AES-XTS, 256-bit key, balanced version

• Moderate resource requirements
• Performance
• Standard Compliance

4 lane 2.5Gbps CSI2-2.1 compliant serial video receiver

• Programmable 1 to 4 lanes, 2.5Gbps per lane
• Pseudo-Random Bit Sequence (PRBS) descrambling
• 16-way deserializer per lane

PCI Express - Configurable PCI Express 4.0 IP

• Compliant with "PCI Expressâ„¢ Base Specification, Rev. 4.0 Version 1.0"
• Compliant with "PHY Interface For the PCI Express, SATA, and USB3.1 Architectures"

1.2V analog IO library for TSMC 65nm

• Optimized for radiation hard (SEU and TID)
• Low capacitance for high speed/high frequency
• Overvoltage tolerant

800 Gigabit Ethernet MAC + PCS

• Two 400GBase-R PCS cores with required modifications and glue logic.
• Includes RS-FEC(544,514) KP4 FEC

eDP1.4/DP1.4 TX IP PHY

• eDP/DP v1.4a compliant Physical layer for Tx
• Consists of two main link channels and one AUX channel
• Supports 1.62Gbps(RBR) to 8.1Gbps(HBR3) bit rate

DesignWare DDR5/4 PHY IP for TSMC N6

• Low latency, small area, low power
• Compatible with JEDEC standard DDR5 SDRAMs up to 4800 Mbps
• Compatible with JEDEC standard DDR4 SDRAMs up to 3200 Mbps

12-bit 1-channel 44 -200 kSPS R/2R DAC

• TSMC CMOS 55nm
• Resolution 12 bit
• Single channel

256x1 Bits OTP (One-Time Programmable) IP, TSMC 0.18μm 1.8V/3.3V Mixed-Signal, General Purpose II

• Fully compatible with TSMC 0.18μm Mixed-Signal, General Purpose II (180MSGPII) process

MIPI CSI-3 Rx Controller

• Hardware configurable compliance with MIPI specification CSI-3 Ver. 1.0
• Provides error detection and retransmission, CPort / virtual channel detection, programmable data extraction, and embedded data separation

Quad core IP platform with integrated Arm security subsystem

• Single channel, video & data processing

Bunch of Wires [BoW] PHY

• Emerging Standard Knowledge
• Flexibly Configurable
• Best in Class PPA

RISC-V 32bit CPU which supports ISO26262 ASIL D

• RISC-V 32bit General Purpose Tiny Core
• ISO26262:2018 ASIL D compliant SEooC IP
• RISC-V Solution by Collaborating with Partners

DDR4/LPDDR4/LPDDR4X PHY

• Multi-interface support. LPDDR4 up to 3200Mbps and DDR4/LPDDR4X up to 4267Mpbs.
• Support LPDDR4X 0.6V VDDQ.

eTCAM (Embedded Ternary Content Addressable Memory IP

• One cycle operation latency (without priority encoder)
• Valid Bit per entry to reduce power
• Valid Bit reset in one cycle support

Multiple Pixel Processing Camera Image Signal Processing Core

• Support RGB Bayer progressive image sensor and Monochrome progressive image sensor
• Support 8 ~ 14 bit input data Bayer

Nano power DC-DC converter in TSMC 22ULL

• Ultra-low quiescent current to ensure minimum current consumption in deep sleep / hibernation mode
• High efficiency at light load to extend battery lifetime

USB 4.0 Gen3X2 and DP1.4 X4 PHY IP with Type-C connector support

• Worldwide smallest USB4.0 PHY IP in 7nm process.
• Fully compliant with Universal Serial Bus USB4.0 Gen3/Gen2/Gen1, USB3.2 Gen2/Gen1 and 2.0 electrical specifications.

High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for TSMC (65nm, 40nm, 28nm, 16nm)

1x64 Bits OTP (One-Time Programmable) IP, GlobalFoundries 22nm FDX 0.8V/1.8V

• Fully compatible with GlobalFoundries 22nmFDX 0.8V/1.8V
• Read voltage: 0.8V+/-10% VDD and 0.8V or 1.8V VDDP.

RISC-V processor with vector extension certified for ISO 26262 ASIL D ready

• Off-loading heavy calculations from microcontrollers
• MIMD-based embedded vector processor
• Certificated standards for automotive functional safety, ISO26262 ASIL D Ready

Aurora 64B/66B IP Core

• Full implementation of Aurora protocol
• Full-Duplex and Simplex Tx operation.
• 64-bits user datapath

Complete Neural Processor for Edge AI

• Designed for Low-Power Neural Network Processing
• Flexible Training Methods
• Scalable Neuron Fabric