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Hardware Security Module (HSM)

• Secure key provisioning
• Secure key storage
• Secure counter

AV1 fixed function HW decoder IP for 4Kp60 4:2:0 10 bit

• Capable of decoding AV1 MAIN profile @L5.1 Main-tier 50Mbps
• Input; 8 or 10 bit, 420 samplings only
• Max Display Resolution: 8192x8192

Process Detector TSMC N5P (For DVFS and monitoring process variation)

• Exclusively digital signalling on ports
• Uses standard digital process layers
• Standard Logic Process

Blockchain Hardware Accelerator

• Wide variety of ECC curves supported (Weierstrass, Edwards, Montgomery, Twisted-Edwards, …)
• Ideal for FPGA/ASIC integration

1 – 33Gbps MP SerDes PHY (PCIe Gen1-Gen5)

• 1 - 33 Gbps continuous operation
• World’s best power, area and latency in segment
• Channel loss support up to 25dB

Transaction-aware embedded cybersecurity solution that can detect, block and record attacks, & prevent propagation

• "Below the operating system" - extra level of security
• Fastest attainable time-to-detection and mitigation

14,080 MAC Deep Neural Network (DNN) Engine for ARC EV7x Processors

• ASIL B and D compliant, or hybrid up to ASIL D
• Integrated safety-critical hardware features
• ECC memories

Power On Reset Circuit in TowerJazz 180nm

• TowerJazz 0.18μm TS18 Standard Logic Process
• Power-On Reset output
• No External Components

GDDR6 Memory Controller

• JEDEC GDDR6 standard JESD250B
• Fast frequency switching
• Flexible Configuration

HBM2E PHY on TSMC 7FF

• JEDEC standard supported: JESD235A & JESD235B
• DFI 4.0 interface compatible
• 8 channels with 1024 DQs per HBM Gen2 Stack

Voltage Monitor with Digital Output TSMC N5 (Multi-domain supply monitoring)

• On-chip Core & I/O supply monitoring
• Low supply voltage alarms
• IR Drop monitoring for core logic

1-33Gbps C2C SerDes PHY

• 1 - 33 Gbps continuous operation
• 1.8 mW/Gbps
• World’s best area and latency in segment

Neural Network Processor for Intelligent Vision, Voice, Natural Language Processing

• Highly efficent neural network inference processor
• Scalable performance from less than 1 TOPS to 100s of TOPS

112G XSR Multi-protocol SerDes PHY

• Supports up to 8 duplex lanes and data rates from 25 to 112 Gbps
• Ultra-low power configurable architecture for D2D and D2OE interfaces

Embedded FPGA

• Low power
• High performance
• Cost savings
• Low risk

Ethernet 1G TSN MAC

• Compliant with IEEE 802.3-2018 specification
• Supports for Full duplex and Half duplex mode
• Supports upto 10M/100M and 1G

TLS Handshake Hardware Accelerator

• RSA, ECC and more
• > 1 GHz in 16nm
• 400-500 MHz on mid-range/high-end FPGA

12-bit 44MS/s ADC

• Samsung 28nm FDS Process
• 1.0V & 1.8V Supplies
• 12-bit SAR ADC

NVM OTP in TSMC (180nm, 130nm, 110nm, 90nm, 65nm, 55nm, 40nm, 28nm, 16nm, 12nm)

10/100 Ethernet PHY

• TSMC 22nm ULP
• support EEE

Deep neural-network accelerator (DNA) AI processor

• Specialized design to take advantage of sparsity in weights and activations for compute and bandwidth reduction

Host Controller IP for xSPI

• Support for multi CMD channels
• Supports JEDEC SFDP (Serial Function Discoverable Parameters)
• Memory mapped – enables BOOT and XIP functionality

Automotive Ethernet MAC IP

• IEEE 802.3 compliant, UNH tested and ISO 26262 ASIL-B qualified
• Enhanced active functional safety features