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Process Node	5nm 7nm 8nm 10nm 12nm 16nm 20nm 22nm 28nm 40nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm
Foundry	GLOBALFOUNDRIES HHGrace IBM LFoundry Renesas Samsung SilTerra SMIC Tower TSMC UMC X-FAB

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APEX 20KC APEX 20KE APEX II Arria Arria 10 Arria 10 GT Arria 10 SoC Arria 10 SX Arria GX Arria GX Arria II Arria II GX Arria II GZ Arria V Arria V GT Arria V GX Arria V GZ Arria V SoC Arria V ST Arria V SX Cyclone Cyclone 10 GX Cyclone 10 LP Cyclone II Cyclone III Cyclone III LS Cyclone IV Cyclone IV E Cyclone IV GX Cyclone Series Cyclone V Cyclone V E Cyclone V GT Cyclone V GX Cyclone V SE Cyclone V SoC Cyclone V ST Cyclone V SX eASIC N2X eASIC N2XT eASIC N3X eASIC N3XS HardCopy HardCopy II HardCopy III HardCopy IV E HardCopy IV GX MAX 10 MAX 10 DF MAX II MAX V Stratix Stratix 10 Stratix 10 GX Stratix 10 MX Stratix 10 SX Stratix 10 TX Stratix GX Stratix II Stratix II GX Stratix III Stratix III E Stratix IV Stratix IV E Stratix IV GT Stratix IV GX Stratix V Stratix V E Stratix V GS Stratix V GT Stratix V GX	Artix-7 Artix-7 -2L Kintex UltraScale Kintex UltraScale+ Kintex-7 Kintex-7 -2L Spartan-3 Spartan-3 XA Spartan-3A Spartan-3A DSP Spartan-3A DSP XA Spartan-3A XA Spartan-3AN Spartan-3E Spartan-3E XA Spartan-6 Spartan-6 -1L Spartan-6 HXT Spartan-6 LX Spartan-6 LXT Spartan-6 XA Spartan-6 XC Spartan-7 Spartan-II Spartan-IIE UltraScale UltraScale+ Virtex UltraScale Virtex UltraScale+ Virtex-4 Virtex-4 FX Virtex-4 LX Virtex-4 SX Virtex-4 XA Virtex-5 Virtex-5 FX Virtex-5 FXT Virtex-5 LX Virtex-5 LXT Virtex-5 SX Virtex-5 SXT Virtex-5 TXT Virtex-6 Virtex-6 -1L Virtex-6 CXT Virtex-6 HXT Virtex-6 LX Virtex-6 LXT Virtex-6 SXT Virtex-6 XC Virtex-7 Virtex-7 -2G Virtex-7 -2L Virtex-7 HT Virtex-7 XT Virtex-7T Virtex-E Virtex-II Virtex-II Pro Zynq UltraScale+ MPSoC Zynq-7000	ispClock ispMACH 4000 LatticeEC/ECP LatticeECP2 LatticeECP2M LatticeECP3 LatticeECP5 LatticeSC LatticeSCM LatticeXP LatticeXP2 MachXO MachXO2 MachXO3 Platform Manager Power Manager II

New Silicon IP

• Multi-PHY Receiver Link Controller

  • SLVS-EC v1.2 / MIPI CSI2 v1-2 / MIPI D-PHY v1-2 Compliant
  • Supports Curious Multi-PHY
  
   
  
  

• Machine Learning processor

  • Increased Performance
  • Improved Efficiency
  • Extended Configurability
  
   
  
  

• Ultra low power AI inference accelerator

  • Energy Efficient
  • High Performance
  • Small footprint
  
   
  
  

• Integrated Secure Element (iSE)

  • Secure boot
  • Life cycle management
  • Secure key storage
  
   
  
  

• 25Gbps Ethernet and CPRI-10 FEC Layer IP Core

  • Proven IP reduces development time and risk
  • Upgrade process as the standard evolves
  • Supports both 25GBASE-KR and 25GBASE-CR PMD interfaces
  
   
  
  

• 12-bit 500MS/s Dual Channel IQ ADC

  • Samsung 8nm LPP Process
  • 0.75V and 1.8V Supplies
  • 12-bit High-Speed SAR Dual-Channel ADC
  
   
  
  

• MIPI C-PHY/D-PHY IP for TSMC 12FFC

  • Compliant with the MIPI D-PHY specification, v2.1
  • 4 Lanes in D-PHY mode up to 4.5 Gb/s per lane
  • Compliant with the MIPI C-PHY specification, v1.2
  
   
  
  

• High performance FFT optimised for Radar

  • 1 clock cycle per point, no gap required between packets
  • Run-time selection of any power of 2 FFT points
  • Run-time selection of froward or inverse transform
  
   
  
  

• MIPI D-PHY Universal IP in Samsung 28FDSOI

  • Supports MIPI® Specification for D-PHY Version 2.1.
  • Consists of 1 Clock lane and up to 4 Data lanes.
  • Supports both high speed and low-power modes.
  
   
  
  

• Wideband LNA with a gain adjustment range from -22 to 20dB

  • TSMC SiGe BiCMOS 180 nm
  • Operating frequency range 500…1500 MHz
  • Low noise figure (2 dB)
  
   
  
  

• Camera SLVS-EC/MIPI D-PHY/CMOS1.8 combo Receiver 2.4G/2.5G/166MHz 8-Lane

  • SLVS-EC ver.1.2 / MIPI D-PHY ver.1-2 compliant
  • Supporting for four kind Differential Input Signals
  • Xtal Input Clock Frequency Selectable
  
   
  
  

• DDR5/4 PHY IP for TSMC 12FFC

  • TSMC 12FFC
  • Low latency, small area, low power
  • Compatible with JEDEC standard DDR5 SDRAMs up to 4800 Mbps
  
   
  
  

Top Silicon IP

• 1

  MIMO Radar Co-processor Engine

  • Low latency, low power and compact
  • Gives ECU headroom for track-to-object recognition and make safety decisions
  
   
  
  
• 2

  Linux capable 64-bit RISC-V processor core with 7-stage pipeline

  • 64-bit RISC-V core
  • Linux capable
  • In-order 7-stage pipeline
  
   
  
  
• 3

  High Performance PLL in TSMC 7nm

  • Fully SCAN enabled
  • Fully customizable to each application
  • Wide operating voltages available for DVFS
  
   
  
  

• 4

  LPDDR5/4/4X PHY IP

  • TSMC 12FFC
  • Low latency, small area, low power
  • Compatible with JEDEC standard LPDDR5 SDRAMs up to 6400 Mbps
  
   
  
  
• 5

  DesignWare MIPI C-PHY/D-PHY IP for TSMC N7

  • Compliant with the MIPI D-PHY specification, v2.1
  • 4 Lanes in D-PHY mode up to 4.5 Gb/s per lane
  • Compliant with the MIPI C-PHY specification, v1.2
  
   
  
  
• 6

  Free-running on-chip oscillator

  • Glitch-free frequency programmability to calibrate out process variations Frequency accuracy as good as 1.5% over voltage, temperature, and process aging after initial calibration
  
   
  
  

• 7

  10-bit SAR ADC TSMC

  • Sampling Rate options: 1 MSps;2 MSps;5 MSps;10 MSps;15 MSps;20 MSps
  • Quick re-configuration to your specification
  • Up to 10-bit resolution
  
   
  
  
• 8

  12-bit 90MS/s ultra-efficient SAR ADC in UMC 28nm HPC+

  • UMC 28nm HPC+
  • Robust Performance
  • Low Power
  • Low Area
  
   
  
  
• 9

  HBM3 Controller

  • Supports HBM3 protocol standard draft JEDEC specification.
  • Compliant with DFI version 4.0 and 5.0 Specification.
  • Supports up to 16 AXI ports with data width upto 512 bits.
  
   
  
  

• 10

  Power Management Unit (2.3 - 3.0V output voltage, load current 150mA)

  • iHP SiGe BiCMOS 0.13 um
  • Output voltage: 2.3 ... 3.0 V
  • Overcurrent indication
  
   
  
  
• 11

  All Digital Fractional-N PLL for Low-Jitter Clocking

  • Frequencies up to 4GHz
  • Low jitter (< 10ps RMS)
  • Small size (< 0.01 sq mm)
  
   
  
  
• 12

  Low Power PLL

  • Lowest power in the industry
  • Smallest area in the industry
  • Customizable in weeks
  
   
  
  

¹ Top Silicon IP Over the Last Two Weeks (Last update: May. 24)

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