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Gate Length	10nm 16nm 20nm 28nm 40nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm
Foundry	GLOBALFOUNDRIES HHGrace IBM LFoundry Renesas SilTerra SMIC TSMC Tower UMC X-FAB

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APEX 20KC APEX 20KE APEX II Arria 10 Arria GX Arria II GX Arria II GZ Arria V GT Arria V GX Arria V GZ Arria V ST Arria V SX Cyclone Cyclone II Cyclone III Cyclone III LS Cyclone IV GX Cyclone V GT Cyclone V GX Cyclone V SE Cyclone V ST Cyclone V SX HardCopy HardCopy II HardCopy III HardCopy IV E HardCopy IV GX MAX II MAX V Stratix Stratix 10 Stratix GX Stratix II Stratix II GX Stratix III Stratix III E Stratix IV Stratix IV GT Stratix IV GX Stratix V E Stratix V GS Stratix V GT Stratix V GX	Artix-7 Artix-7 -2L Kintex UltraScale Kintex UltraScale+ Kintex-7 Kintex-7 -2L Spartan-3 Spartan-3 XA Spartan-3A Spartan-3A DSP Spartan-3A DSP XA Spartan-3A XA Spartan-3AN Spartan-3E Spartan-3E XA Spartan-6 Spartan-6 -1L Spartan-6 HXT Spartan-6 LX Spartan-6 LXT Spartan-6 XA Spartan-6 XC Spartan-7 Spartan-II Spartan-IIE UltraScale UltraScale+ Virtex UltraScale Virtex UltraScale+ Virtex-4 Virtex-4 FX Virtex-4 LX Virtex-4 SX Virtex-4 XA Virtex-5 Virtex-5 FX Virtex-5 FXT Virtex-5 LX Virtex-5 LXT Virtex-5 SX Virtex-5 SXT Virtex-5 TXT Virtex-6 Virtex-6 -1L Virtex-6 CXT Virtex-6 HXT Virtex-6 LX Virtex-6 LXT Virtex-6 SXT Virtex-6 XC Virtex-7 Virtex-7 -2G Virtex-7 -2L Virtex-7 HT Virtex-7 XT Virtex-7T Virtex-E Virtex-II Virtex-II Pro Zynq UltraScale+ MPSoC Zynq-7000	ispClock ispMACH 4000 LatticeEC/ECP LatticeECP2 LatticeECP2M LatticeECP3 LatticeSC LatticeSCM LatticeXP LatticeXP2 MachXO MachXO2 MachXO3 Platform Manager Power Manager II

New Silicon IP

• 12-Bit 20MS/s Dual Current Steering DAC

  • 55nm SMIC eFlash Process, 6 Metals Used
  • 1.8V and 1.2V Supplies
  • Sampling Rate up to 20MS/s
  
   
  
  

• 10G PHY for PCIe 3.0, TSMC 16nm

  • TSMC 16FFC x4 for Automotive, North/South (vertical) poly orientation
  
   
  
  

• LPDDR4 SDRAM Controller

  • Maximizes bus efficiency via Look- Ahead command processing, Bank Management and Auto-Precharge
  • Minimal latency achieved via parameterized pipelining
  
   
  
  

• NVMe-to-NVMe Bridge

  • Fully compliant to the NVM Express 3 industry specification
  • Automated initialization process with PCIe Hard Block
  • Automated command submission and completion
  
   
  
  

• USB 3.0 femtoPHY - SS 14LPP x1 OTG

  • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
  • Supports the USB 2.0 480 Mbps protocol and data rate (High-Speed)
  
   
  
  

• MIPI D-PHY Universal Lane 16FFC IP for Automotive

  • Supports MIPI® Specification for D-PHY Version 1.2.
  • Optimized for Automotive applications.
  • Fully functional -40°C to 150°C Tj.
  
   
  
  

• Bandgap Reference - TSMC 90nm LP

  • 90nm TSMC Logic LP Flash, 5 Metals Used
  • (No Analog Options) with Deep-Nwell
  • 3.0V ~ 3.6V Power Supply Voltage
  
   
  
  

• K-Best (4X4) MIMO Decoder

  • Fixed Depth K-Best Decoder (K=16)
  • Achieves close-to ML BER performance
  
   
  
  

• 16nm LVDS Receiver IO

  • TSMC 16nm FFC CMOS process using 7-2-2 Metal Stack
  • Uses LVT, SVT core and 1.8V SVT transistors.
  • Targeted for flip-chip packages
  
   
  
  

• 250Mbps to 12.7Gbps Multiprotocol SerDes PMA

  • Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
  • Extremely low jitter suitable for Enterprise SerDes applications
  
   
  
  

• DPDK-aware FPGA/GPP data mover

  • Line rate agnostic: Operates at any line rate, including 1/5/10/25/40/50/100/400 GbE
  • Up to 150 Gbps and 120 Mpps with a contemporary PCIe Gen3x16 interface, Gen4 Ready
  
   
  
  

• 12-Bit 160MS/s Dual Current Steering DAC

  • 28nm GlobalFoundries SLP Process, 7 Metals Used
  • 1.8V and 1.0V Supplies
  • Sampling Rate up to 160MS/s
  
   
  
  

Top Silicon IP

• 1

  Compact Implementation of the RISC-V RV32IMC ISA

  • RISC-V 32 bit ISA (RV32)
  • Integer Instruction Set (I)
  • Compressed Instruction Set (C)
  
   
  
  
• 2

  Low Power Multiprotocol SerDes PMA

  • Very wide CDR range - operates with data rates from 0.6Gbps to 4.0Gbps
  • Compatible with JESD204A, JESD204B, OIF-CEI-6G-SR, CPRI, SGMII, XAUI and V-by-One
  
   
  
  
• 3

  Image Signal Processing IP Solution - CARPO

  • Max Resolution : Full-HD (16:9) 1920(H) x 1080(V)
  • Max Frame Rate : 60 FPS @ 2MP
  
   
  
  

• 4

  IEEE 802.1AS Hardware Protocol Stack

  • Complete IEEE 802.1AS hardware stack enabling rapid development of time-aware AVB/TSN nodes
  • IEEE 802.1AS Hardware Stack
  
   
  
  
• 5

  Floating-point (IEEE 754) IP based on Arria 10 and Stratix 10 FPGAs

  • FFT size: Any size power-of-two or non-power-of-two
  • Dynamic Range: IEEE754 single precision floating point
  
   
  
  
• 6

  MIPI CSI2 rev 2.0 Transmitter / Controller

  • One clock lane, and from 1 to 8 data lanes
  • Simple interface – legacy parallel-video input, augmented by an Early-HD signal
  
   
  
  

• 7

  BLE 5 / 15.4 (0.5mm2) RF IP

  • BLE 5 Compliant
  • ZigBee 3.0 Compliant
  • 0.5mm2 die size in TSMC 40LP
  
   
  
  
• 8

  12-Bit 1 MS/s DAC with voltage output

  • Resolution: 12 bit
  • Conversion rate: 1 MS/s
  • Power consumption: 15 mW @ 3.3 V
  
   
  
  
• 9

  NB-IoT Protocol stack and layer

  • Hand-code in 'C' for lowest footprint and latency
  • AS and L1-control as required
  
   
  
  

• 10

  LPDDR4 multiPHY V2 - SS 10LPP

  • Supports JEDEC standard LPDDR4, LPDDR3, DDR4, DDR3, DDR3L (1.35V DDR3), and DDR3U (1.25V DDR3) SDRAMs
  
   
  
  
• 11

  LPDDR3/4 DRAM Memory Controller

  • Fully compliant with JEDEC JESD209-3C and JESD209-4B
  • Compliant with DFI3.1 and DFI4.0 PHY specifications
  
   
  
  
• 12

  K-Best (2X2) MIMO Decoder

  • Fixed Depth K-Best Decoder (K=16)
  • Achieves close-to ML BER performance
  
   
  
  

¹ Top Silicon IP Over the Last Two Weeks (Last update: Jul. 23)

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