Browse >>

Search for Silicon IP

 

Additional options:

On a Specific ASIC Technology

On a Specific FPGA Technology

---

Process Node	5nm 7nm 8nm 10nm 12nm 16nm 20nm 22nm 28nm 40nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm
Foundry	GLOBALFOUNDRIES HHGrace IBM LFoundry Renesas Samsung SilTerra SMIC Tower TSMC UMC X-FAB

---

APEX 20KC APEX 20KE APEX II Arria Arria 10 Arria 10 GT Arria 10 SoC Arria 10 SX Arria GX Arria GX Arria II Arria II GX Arria II GZ Arria V Arria V GT Arria V GX Arria V GZ Arria V SoC Arria V ST Arria V SX Cyclone Cyclone 10 GX Cyclone 10 LP Cyclone II Cyclone III Cyclone III LS Cyclone IV Cyclone IV E Cyclone IV GX Cyclone Series Cyclone V Cyclone V E Cyclone V GT Cyclone V GX Cyclone V SE Cyclone V SoC Cyclone V ST Cyclone V SX eASIC N2X eASIC N2XT eASIC N3X eASIC N3XS HardCopy HardCopy II HardCopy III HardCopy IV E HardCopy IV GX MAX 10 MAX 10 DF MAX II MAX V Stratix Stratix 10 Stratix 10 GX Stratix 10 MX Stratix 10 SX Stratix 10 TX Stratix GX Stratix II Stratix II GX Stratix III Stratix III E Stratix IV Stratix IV E Stratix IV GT Stratix IV GX Stratix V Stratix V E Stratix V GS Stratix V GT Stratix V GX	Artix-7 Artix-7 -2L Kintex UltraScale Kintex UltraScale+ Kintex-7 Kintex-7 -2L Spartan-3 Spartan-3 XA Spartan-3A Spartan-3A DSP Spartan-3A DSP XA Spartan-3A XA Spartan-3AN Spartan-3E Spartan-3E XA Spartan-6 Spartan-6 -1L Spartan-6 HXT Spartan-6 LX Spartan-6 LXT Spartan-6 XA Spartan-6 XC Spartan-7 Spartan-II Spartan-IIE UltraScale UltraScale+ Virtex UltraScale Virtex UltraScale+ Virtex-4 Virtex-4 FX Virtex-4 LX Virtex-4 SX Virtex-4 XA Virtex-5 Virtex-5 FX Virtex-5 FXT Virtex-5 LX Virtex-5 LXT Virtex-5 SX Virtex-5 SXT Virtex-5 TXT Virtex-6 Virtex-6 -1L Virtex-6 CXT Virtex-6 HXT Virtex-6 LX Virtex-6 LXT Virtex-6 SXT Virtex-6 XC Virtex-7 Virtex-7 -2G Virtex-7 -2L Virtex-7 HT Virtex-7 XT Virtex-7T Virtex-E Virtex-II Virtex-II Pro Zynq UltraScale+ MPSoC Zynq-7000	ispClock ispMACH 4000 LatticeEC/ECP LatticeECP2 LatticeECP2M LatticeECP3 LatticeECP5 LatticeSC LatticeSCM LatticeXP LatticeXP2 MachXO MachXO2 MachXO3 Platform Manager Power Manager II	Axcelerator eX Fusion IGLOO IGLOO nano IGLOO PLUS IGLOO2 MX Polarfire ProASIC3 ProASIC3 nano ProASIC3E ProASIC3L ProASICPLUS RT ProASIC3 RTAX-S/SL/DSP RTG4 RTSX-SU SmartFusion SmartFusion2 SX-A

New Silicon IP

• Bluetooth Low Energy v5.2 IP in TSMC40LP

  • Silicon ready design
  • Industry leading sensitivity
  • Low power consumption
  
   
  
  

• 10-bit SAR ADC TSMC

  • Sampling Rate options: 1 MSps;2 MSps;5 MSps;10 MSps;15 MSps;20 MSps
  • Quick re-configuration to your specification
  • Up to 10-bit resolution
  
   
  
  

• Ultra-low Jitter Fractional-N Frequency Synthesizer PLL (5nm - 180nm)

  • Jitter-Power optimized to meet PCIe1-5 reference clock requirements - replaces 300mW/$2.50 clock chip
  • Low area on chip -- keepouts = DRC limit in most cases
  
   
  
  

• 6-bit, 1 GSPS High Performance AFE in 28nm CMOS

  • 6-bit resolution, variable update rate up to 1 GSPS
  • Fully differential current output, fully specified from -40C to 125C
  • Ultra low power dissipation
  
   
  
  

• Lossless Video Compression (HLVC) Encoder

  • True mathematically lossless (bit-exact) compression
  • Supports lossless compression of a wide variety of RAW data
  
   
  
  

• ARC EM22FS safety processor

  • Dual-core lockstep safety processor supports ISO 26262 automotive safety standards
  
   
  
  

• Power Line Communications, PLC, Transceiver, N-PLC, G3-PLC, Prime, IEEE, Sunspec

  • Configurable power line communications modem
  • Data rates up to 400kbps
  • Configurable operational bands (5 - 500 kHz)
  
   
  
  

• Arm Cortex-M35P

  • Improve ML and DSP Performance
  • Accelerate Time to Market
  • Simplify Software Development
  
   
  
  

• eFPGA Tile with power management for TSMC 40ULP & 40LP

  • Metal Stack: 7 layer metal
  • Nominal Supply Voltages (Vj): 1.1 V
  • Junction Temperature (°C): −40 to 125
  
   
  
  

• Lossless Video Compression (HLVC) Decoder

  • True mathematically lossless (bit-exact) compression
  • Supports lossless compression of a wide variety of RAW data
  
   
  
  

• 12-bit ultra-low power single-ended SAR ADC

  • Sample rate from 100kSPS to 1MSPS
  • Ultra-low power
  
   
  
  

• Machine Learning Processor

  • Partner Configurable
  • Extremely Small Area
  • Single Toolchain
  
   
  
  

Top Silicon IP

• 1

  56G PAM4 SerDes PHY

  • Samsung Foundry 10 nm low-power CMOS
  • Supports a maximum LR channel loss of -35dB@14 GHz (ball-toball)
  • Supports a maximum -50dB@14 GHz crosstalk
  
   
  
  
• 2

  Real-time multi-standard Decoder

  • HEVC, H.264, VP9, AVS2 and AV1 Multi format Decoder for UHD (up to 8K) 4:2:0 10bit
  • Ideal Solution for Ultra HD Devices.
  • Superior Error resilience, concealment, and reporting.
  
   
  
  
• 3

  RISC-V 64-bit Processor

  • RISC-V 64IMC, with AFDN (ie GCN) to be released
  • RISC-V standard PLIC
  • RISC-V standard PMP (physical memory protection)
  
   
  
  

• 4

  USB Type-C 40 Gb/s Multi-Protocol Switch and Bi-Directional Bit-Level Retimer

  • USB4 Gen2, Gen3
  • USB3.2 Super Speed+
  • DP1.4a (8.1 / 5.4 / 2.7 / 1.62 Gb/s) and x1, x2, x4
  
   
  
  
• 5

  High-performance 64-bit RISC-V architecture multi-core processor with AI vector acceleration engine

  • Instruction set: RISC-V RV64GC/RV 64GCV;
  • Multi-core: Isomorphic multi-core with 1 to 4 optional clusters. Each cluster can have 1 to 4 optional cores;
  
   
  
  
• 6

  PCIe 5.0 IP in Samsung 7nm

  • Physical Coding Sublayer (PCS) block with PIPE interface
  • Supports PCIe 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
  
   
  
  

• 7

  MIPI D-PHY Universal 4 Lane 2.5Gbps

  • Supports MIPI Alliance Specification for D-PHY Version 2.1
  • Backward compatible with MIPI Specifications for D-PHY v1.2, and v1.1
  • Consists of 1 Clock lane and 4 Data lanes
  
   
  
  
• 8

  High Throughput Elliptic Curve Cryptography hardware acceleration Core

  • Supports any EC over GF(p) of the simplified Weierstrass form
  • EC Digital Signature Algorithm (ECDSA) Signature/Verification1 and EC Scalar Multiplication (ECSM)
  
   
  
  
• 9

  24-Bit Continuous Time Sigma Delta Audio ADC

  • TSMC 40nm ULP Process
  • 1.1V & 1.8V Supplies
  • Continuous-Time Sigma-Delta ADC
  
   
  
  

• 10

  Automotive Ethernet MAC IP

  • IEEE 802.3 compliant, UNH tested and ISO 26262 ASIL-B qualified
  • Enhanced active functional safety features
  
   
  
  
• 11

  112Gbps Multi-Rate Long-Reach PAM-4 SerDes

  • Available 7nm FinFET CMOS Processes
  • 112/56Gbps PAM-4 or 56/28/10Gbps NRZ data rates
  • Power-optimized for LR and MR links
  
   
  
  
• 12

  Time Sensitive Networking (TSN) Single Port End Node core

  • Up to 8 different priority queues, with freely definable VLAN priorities
  • Up to 8 phases per cycle according to priority queues
  
   
  
  

¹ Top Silicon IP Over the Last Two Weeks (Last update: Feb. 23)

IP Provider: Give the best exposure to your IPs, by listing your products for free in the world's largest Silicon IP catalog (8,000 products from more than 400 companies)

© 2020 Design And Reuse

All Rights Reserved.

No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.