90nm OTP Non Volatile Memory for Standard CMOS Logic Process
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New Silicon IP
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Securyzr™ neo Core Platform - One core, multiple products
- Secure Boot
- Firmware update in the field
- Secure key storage
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MIPI I3C Controller and Target fully featured IP solution
- Fully compliant with MIPI I3C v1.1.1 Specification
- TCRI v1.0 Compliant
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Centralized Network Configurator (CNC) for TSN nodes such as endpoints and Switches
- Read static topology from YANG compliant custom XML file
- Read dynamic Traffic Provision Request (TPR) from IEEE 802.1Qdj YANG compliant file
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Remote Temperature Sensor
- 4nm CMOS device technology
- Dual power supply: 1.2V±10%, 0.75V±10%
- Operating junction temperature(Tj): -40℃ to125℃
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Ultra Low Power AI core
- Ultra-low standalone NPU core uW to mW active power
- Supports power islands for minimal standby power
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PCIe 6.0 PHY IP for TSMC N5
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 6.0, encoding, backchannel initialization
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Low jitter, ultra-low power (<950uW) ring-oscillator-based PLL-2.4GHz
- Ultra-low jitter (less than 1ps rms jitter)
- Low power (Less than 950uW)
- Ultra-small area (0.007sq mm)
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Ultra-low-power AI/ML processor and accelerator
- Allows complex inference at the very edge, at the sensor, even in battery-operated or energy harvesting devices.
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WiSUN Sub-GHz 433, 868, 915MHz Transceiver IP
- Multi-Band 433/868/915MHz
- Supply Voltages Core: 1.0-1.2V, I/O: 2.0-3.6V
- Junction Temperature Range -40 to +125C
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0.75V Power On Reset
- 4nm Low Power Plus (LN04LPP) CMOS device technology
- Single power supply: 0.675V to 0.825V
- Operational Junction Temperature(Tj): -40℃ to 125℃
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2-stage Power Amplifier 14.5GHz ultra-efficient Dual-Drive™ PA
- 2-stage PAEmax = 50%
- PA-stage DEmax = 60%
- Psat = 20dBm
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112G Ethernet PHY IP for TSMC N6
- Supports full-duplex 1.25 to 112Gbps data rates in 1, 2, and 4 lanes
- Enables 100G, 200G, 400G, 800G
Top Silicon IP
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1
UCIe Die-to-Die Chiplet Controller
- AXI over UCIe Streaming Protocol
- Link Error Detection and Retry Feature
- APB for Controller Control
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2
16bit 2Msps SAR General Purpose ADC in SMIC 40nm
- 16-bit SAR ADC Process: SMIC 40LL CMOS process
- Typical sample rate of 16bit mode is 2MSps, Max sample rate up to 4MS/s
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3
40G UCIe PHY for organic substrate standard packages
- Data rates up to 40Gbps per pin while also compliant with the latest UCIe specification
- Self-contained hard macro
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4
8-stage superscalar processor that supports ISO 26262 ASIL (Automotive Safety Integrity Level) -D level functional safety for automotive applications
- 32-bit in-order dual-issue 8-stage pipeline CPU architecture
- AndeStar™ V5 Instruction Set Architecture (ISA)
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5
6.6GHz Integer PLL
- 5nm Low Power Enhanced (LN05LPE) CMOS device technology
- Dual power supply of 1.2V±10% and 1.2V+10% ~ 0.5V-5%
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6
Deskew Frequency Synthesizer PLL
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7
Bluetooth Dual Mode PHY IP
- Game-changing autonomy on a cell battery
- Industry-leading budget link for reliable audio streaming
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8
Fractional-N Frequency Synthesizer PLL
- Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
- Input & output frequency ranges greater than 1000:1
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9
BT Dual Mode v6.0 RF PHY IP in TSMC 22nm with Channel sounding
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10
Low Phase Noise, High-performance Digital LC PLL
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11
Integer-N Frequency Synthesizer PLL
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12
32kHz Low-bandwidth Frequency Synthesizer PLL
- Input frequency range includes 32.768kHz
- Output frequency range: <10MHz to >200MHz
- Ultra-fast start-up. Frequency calibration ensures Fout is within 2% in <1.4ms from cold start
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