Search for Silicon IP

13-bit, 80 MSPS Analog-to-Digital Converter IP Block

• 13-bit resolution
• 80 MSPS sampling speed
• Bandwidth: 2 MHz around Fs/4

MIPI CSI-2

• (SROI) Smart Region of Interest,
• (USL) Universal Serial Link,
• (AOSC) Always-On Sentinel Conduit,

DVB-S2X Wideband LDPC BCH Encoder IP Core

• Compliant with ETSI EN 302 307’
• Compliant with ETSI EN 302 307-2’
• Supports BCH-LDPC all code rates for digital video broadcasting

Register File with low power retention mode and 3 speed options

• Ultra-Low Leakage: High VT (HVT) and low leakage HVT (LLHVT) devices used with source biasing to minimize standby currents while operating at low voltage.

MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP (8.0Gsps/trio, 6.5Gbps/lane) in TSMC 16FFC

• Compatible with both C-PHY v2.1 and D-PHY v3.0 specifications for added flexibility.

PCIe 5.0 PHY IP for TSMC N5

• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization

5V Library for Generic I/O and ESD Applications TSMC 12nm FFC/FFC+ process.

• Targets up to 8A applications
• >8kV HBM
• Silicon Proven

8Kx8 Bits OTP (One-Time Programmable) IP, MXI- 0.18μm 1.8V/5V Logic/BCD Process

• Fully compatible with MXIC 0.18µm BCD process
• High capacity: 64 kbits OTP macro
• Low voltage: 1.8 V ± 10% read and 3.70 V ± 5% program

12-bit, 5 GSPS ADC on GF 22FDX

• 12 bit resolution
• 5 GSPS sampling rate
• 6 GHz Input Bandwidth

DiFi IP core

• Supports: Signal Data, Flow Control, Signal and Version Context Packets
• Integrates Easily with UDP/IP Ethernet Stack through the AXI interface

Special Purpose Low (Statistical) offset Operation Amplifier

• Power Supply : 1.8 V
• Open loop gain : 109 dB
• PSRR : 98 dB@ 1 KHz

PCIe 6.0 PHY IP for TSMC N4P

• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 6.0, encoding, backchannel initialization

TSMC FPD-Link / OpenLDI / LVDS forwarded clock SERDES Link

• Universal LVDS-based interfaces supporting variety of Tx and Rx configurations.

Dilithium IP Core

• Supports sign and verify operations.
• Supports all three Dilithium modes.
• Has fully stallable input and output interfaces.

PCIe GEN6 PHY

• Supports PRBS (Pseudo Random Binary Sequence) testing including loopback modes

AV1/HEVC/AVC/VP9 Video Codec HW IP 8K30fps@550MHz

• High-quality encoding
• Improved bandwidth efficiency
• Low delay encoding

LPDDR Controller for LPDDR5X, LPDDR5 and LPDDR4X

• Complete, integrated LPDDR5X/5/4X solution from a single vendor when combined with Synopsys’ LPDDR5X/5/4X PHY IP

KYBER IP Core

• supports encapsulation and decapsulation operations
• supports all modes K=2,3,4.
• is compliant with Kyber specification round 3.

Post-Quantum Cryptography - PQC Key Encapsulation IP Core (ML-KEM)

• FIPS 203 compliant
• Supports ML-KEM 512/768/1024 sets
• Self-contained engine with a minimal attack surface

DDR4 Memory Controller

Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more

• Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
• Extremely low jitter suitable for Enterprise SerDes applications

High Bandwidth Memory 3 (HBM3/3E) IP optimized for Samsung SF4X

• Supports up to 9.6 Gbps/pin
• Supports 16 channels (32 pseudo channels)
• Supports AXI4 mainband and AXI4-Lite sideband interfaces

Multi-protocol SerDes PMA in FDSOI (GF22FDX FDX 22FDX) - PCIe1 PCIe2 PCIe3 PCIe4 and more

8-bit/12-bit JPEG Codec IP upto 64Kx64K

• Compliant with the Extended sequential DCT mode of ISO/IEC 10918-1 JPEG standard, the WAVEJ can also support motion JPEG streams with varied color formats supporting resolutions up to 64K x 64K.