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Modern, high performance Audio DSP, optimized for far-field noise reduction and Artificial Intelligence speech recognition

• Octal 16x16 MACs
• Quad 32x32 MACs
• 5-way VLIW

High capacity TSN Ethernet Switching

• High Performance
• Highly Configurable
• Richly featured

12-bit 50MS/s ADC - TSMC 40nm LP

• TSMC 40nm LP (Low-Power Process)
• 1.1V and 2.5V Supplies
• 12-bit SAR ADC

DDR4/3 PHY IP in Samsung 8LPP

• Low latency, small area, low power
• Compatible with JEDEC standard DDR4 SDRAMs up to 3200 Mbps
• Compatible with JEDEC standard DDR3 or DDR3L SDRAMs up to 2133 Mbps

Neoverse N1 CPU

• Revolutionary Compute Performance
• Infrastructure-Specific Features
• Extreme Scalability and Diversity

IMG A-Series AXE Graphics Processor

• Area-optimised, fillrate-focused designs for cost-sensitive devices

ARC HS46FS and HS47DFS Functional Safety Processors

• High-speed, dual-issue, 10-stage pipeline
• Up to 16 MB instruction and data close coupled memory (CCM)
• 4 KB to 64 KB L1 instruction and data cache

Low Drop Out Voltage Regulator 25mA

• 40nm TSMC Logic LP Process, 8 Metals Used with Deep-Nwell
• 2.25V – 3.6V Input Voltage
• 0.9V – 2.8V 3% Output Voltage

Video Codec IP using RAW input­ (CFA)

• Low complexity for ASIC & FPGA
• No external DDR (optional)
• Extreme low latency

Modern Audio DSP, designed for battery operated, high-performance, audio and voice applications

• Quad 16x16 MACs
• Dual 32x32 MACs
• 4-way VLIW

Safety Vision Processor for Automotive ASIL B/D Applications with 4 Vector Processing Units – ARC EV74FS

• ASIL B and D compliant, or hybrid up to ASIL D
• Integrated safety-critical hardware features
• ECC memories

MIPI C-PHY CSI-2 TX+ for TSMC 40ULP

• Supports MIPI Specification for C-PHY Version 1.1
• 80 Msps to 2.5 Gsps data rate in high speed mode

Die-to-Die PHY IP in TSMC N7

• Offers leading performance, power, and area / beachfront per terabit
• Includes 16 lanes of NRZ and PAM-4 transmitters or receivers

Elliptic Curve Accelerator

• Operation over any prime field GF(p)
• ECDSA, EdDSA and ECDH functionality
• EC arithmetic operations: addition, doubling and scalar

Safety Vision Processor for Automotive ASIL B/D Applications with 4 Vector Processing Units – ARC EV74FS

• ASIL B and D compliant, or hybrid up to ASIL D
• Integrated safety-critical hardware features
• ECC memories

CXL Controller with AMBA Bridge

• Fully supports the CXL 1.0 and 1.1 specifications
• Supports PCI Express 5.0 mode with 32 GT/s and x16 link width

Video Codec IP using RAW input­ (CFA)

• Low complexity for ASIC & FPGA
• No external DDR (optional)
• Extreme low latency

Deterministic Random Bit Generator (DRBG)

• NIST 800-90A/B/C compliant
• Health test
• AES-CTR based (CTR_DRBG)

Deep neural-network accelerator (DNA) AI processor

• Specialized design to take advantage of sparsity in weights and activations for compute and bandwidth reduction

12-bit 160MS/s Dual Channel ADC

• SMIC 28nm PS Process
• 1.05V and 1.8V Supplies
• 12-bit Dual-Channel High-Speed SAR ADC

Always-on Voice Activity Detection interfacing with analog microphones

JESD207 RFIC IP

• Compliant with JESD207 specification.
• Full JESD207 RFIC functionality.
• Supports half duplex data transfer.

eSPI Controller

• Compliant with eSPI rev.1.0 specification
• Supports Master and Slave Modes

SM4-XTS engine

• Widebus interface
• Key size: 128 bits
• Key scheduling in hardware