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MIPI DSI-2 with VESA DSC

• Fully compliant to MIPI and VESA standards
• Small footprint
• Code validated with HAL and 0-in-CDC

IEEE802.11n/ac/ax Wi-Fi LDPC Encoder + Decoder

• High throughput design.
• Frame-to-frame on-the-fly configuration.

Video Design Framework for Multi-camera Vision Applications

• Complete video design framework for embedded multi-camera vision applications

ASIL-D Certified subset of Standard C Library suitable for safety critical applications

• ASIL-D certified software that implements external software-based hardware safety mechanism provided for EM22FS, HS4xFS, EV7xFS, VPX5FS processors

3.3 - 4.2V to 0 - minus 100V step-down DC/DC converter

• XFAB XT018
• Input Voltage Range: 3.3V to 4.2V
• Output Voltage: 0 to minus 100V

LPDDR5x/5/4x Memory Controller

• Intensive DRAM Utilization
• Ultra Low Power Consumption
• Extremely Low Latency
• Safety & Security

eSPI & SPI Master Controller w/FIFO

• Master eSPI and standard Master SPI Modes
• Master SPI Modes

MST Topology Management Stack

• DisplayPort 1.4/2.0 compliant
• Fully portable embedded C
• Auto enumeration and stream management

SMPTE 2110-22 Sub-system (TX/RX) IP-cores for JPEG XS video over RTP encapsulation

• RTP Packetization and depacketization compliant with the IETF RTP Payload Format for ISO/IEC 21122 (RFC 9134 / JPEG XS) and recommendations of the VSF TR08.

MIPI SPMI 2.0 Device

• Fully compliant to MIPI standard
• Small footprint
• Code validated with Spyglass

LPDDR5X/5/4X Controller

• Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
• Multiport Arm® AMBA® interface (AXIâ„¢4 / AXIâ„¢ 3) with managed QoS or single-port host interface to the DDR controller

General Purpose Fractional-N PLL in TMSC 16FFC

• Low jitter (< 18ps RMS)
• Small size (< 0.005 sq mm)
• Low Power (< 1.7mW)

RISC-V CPU IP With ISO 26262 Full Compliance

• AndeStarâ„¢ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
• Floating point extensions
• Bit-manipulation extensions

2.5D Multi-Core Raster & Vector Graphics Processor for low-power SoCs with Microcontroller

• Programmable Shader engine with a VLIW instruction set
• Command list based DMAs to minimize CPU overhead
• Primitive Rasterizer

High Performance HBM, HBM3 Memory Controller

• DRAM Supports
• High Performance
• Low Power Consumption

Process, Voltage, and Temperature Monitor

• ± 4C temperature accuracy without trim
• ± 1C temperature accuracy after single room temperature trim
• 0.011C temperature resolution

UCIe Controller

• Low Latency controller for UCIe-based die-to-die connectivity
• Includes Die-to-Die Adapter layer and Protocol layer

Very Low Area Fractional-N Frequency Synthesizer PLL

• Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
• Input & output frequency ranges greater than 1000:1

Fractional-N PLL for Performance Computing in TSMC N5/N4

• Fractional multiplication with frequency up to 5GHz
• Low jitter (< 10ps RMS)
• Small size (< 0.003 sq mm)

128-bit vector word length ARC VPX2 DSP IP with integrated hardware safety features for automotive

• Four-way VLIW combining scalar and vector operations
• 128-bit, 256-bit and 512-bit vector word lengths
• 8, 16, and 32-bit integer SIMD engines

PCIe 6.0 SerDes PHY

• Complete SerDes subsystem solution with Rambus PCIe 6.0 controller core
• PIPE 6.0-compliant interface for Rambus PCI Express 6.0 Controller

APB SPI (Serial Peripheral Interface) master and slave

PHY IP for LPDDR5 on Samsung 14nm

• Compliant with PHY standards
• Flexible Configuration
• Maximum data rates

PCI Express 6.0 PHY IP on N5

• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 6.0, encoding, backchannel initialization
• Supports PCIe Lane Margining at Receiver