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LPDDR5/4/4X PHY IP for TSMC N6

• Supports JEDEC standard LPDDR5, LPDDR4 and LPDDR4X SDRAMs
• Support for data rates up to 6400Mbps

1-56/112G ePHY IP

• Multi-protocol ePHY IP supports 1-56/112Gbps data rates
• Low-Jitter Transmitter with 8-tap de-emphasis FIR

Dual-CORE HEVC/H.265 & H.264 encoder for 4K60fps (up to 8K60fps)

• Frame buffer compression (called CFrame) for bandwidth saving
• Additional secondary AXI for bandwidth reduction

Power Management Unit

• iHP SG25H4 SiGe BiCMOS 0.25 um
• Bandgap voltage source 1.12V
• Low drop out voltage regulator

Bandgap Reference for SoC Integration and Hardware Security (22 nm, high-accuracy of ±1%)

• vdd_hv Performance: 1.62 V to 1.98 V
• vdd_hv Functional: 1.55 V to 2.05 V
• vdd_core_lv: 0.585 V to 0.99 V

64-Bit 8-stage superscalar processor that supports RISC-V specification, including GCN

• 64-bit in-order dual-issue 8-stage pipeline CPU architecture
• AndeStarâ„¢ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology

Graphics Processing Unit (GPU) IP

• 4 GC8400 cores
• Vulkan 1.1
• OpenGL ES 3.2 (AEP)

PHY IP for PCIe 5.0 in TSMC N5

• Supports all required features of the PCIe® 5.0, 4.0, 3.1, 2.1, 1.1, and PIPE specifications
• x1, x2, x4, x8, x16 lane configurations with bifurcation

Low Drop Out 250mA Voltage Regulator TSMC 40nm

• 40nm TSMC Logic LP Process, 7 Metals Used
• (No Analog Options) with Deep-Nwell
• 2.0V - 3.6V Input Voltage

IMG Series4 Neural Network Accelerator (NNA)

• Imagination Tensor Tiling
• Lossless weight compression
• Low latency

MIPI I3C Basic Slave Controller and I3C-to-AHB Bridge

• I3C Basic Slave and I3C-to-AHB Bridge
• Minimal host overhead
• Small silicon footprint

GF12LP+ Lowest power and lowest area PLL in the industry. Customizable in weeks.

• Lowest power in the industry 0.5mW - 1.5mW
• Smallest area in the industry

RISC-V-based SoC template

• Based on the picorv32 RISC-V CPU
• (Re)programmable via UART

Arm Cortex-A78C CPU

• Secure and Scalable Performance for Next-Generation On-The-Go Devices

Security Enclave IP based on RISC-V

• Secure Boot
• Firmware update in the field
• Secure key storage

64-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux

• Performance
• Memory Protection (PMP), and programmable Physical Memory Attribute (PMA)
• Flexibility

Machine Learning Processor

• Extending Performance and Efficiency
• Flexible Integration
• Unified Software and Tools

Controller IP for Bluetooth 5.2, Thread, and Zigbee

• Compliant with the Bluetooth 5.1, Bluetooth mesh, Thread, and Zigbee specifications
• Optimized for power, area and memory footprint

Audio I2S-TDM Transceiver

• Full duplex operation for maximum 10 receive pins and 10 transmit pin
• High-channel count, for example, 86 48KHz/24-bit channels for a 100MHz bit clock frequency

SDR (100MHz -2.6GHz) RF IP

• Frequency Range: 100MHz - 2.6GHz
• Bandwidth Range: 180KHz ~ 20MHz
• Supports HD-FDD/TDD modes.

IMG Series4 Neural Network Accelerator (NNA)

• Imagination Tensor Tiling
• Lossless weight compression
• Low latency

eUSB2 PHY for TSMC N5

• Compliant with eUSB2 specification rev 1.1 Can be used in USB Host, Device, and Dual Role applications

5G/WiFi LDPC Decoder

• Layered LDPC decoder for 5G and WiFi (802.11n, 802.11ac, 802.11ax).

AHB Quad SPI Controller with Execute in Place (70115)