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MST Topology Management Stack

• DisplayPort 1.4/2.0 compliant
• Fully portable embedded C
• Auto enumeration and stream management

SMPTE 2110-22 Sub-system (TX/RX) IP-cores for JPEG XS video over RTP encapsulation

• RTP Packetization and depacketization compliant with the IETF RTP Payload Format for ISO/IEC 21122 (RFC 9134 / JPEG XS) and recommendations of the VSF TR08.

MIPI SPMI 2.0 Device

• Fully compliant to MIPI standard
• Small footprint
• Code validated with Spyglass

LPDDR5X/5/4X Controller

• Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
• Multiport Arm® AMBA® interface (AXIâ„¢4 / AXIâ„¢ 3) with managed QoS or single-port host interface to the DDR controller

General Purpose Fractional-N PLL in TMSC 16FFC

• Low jitter (< 18ps RMS)
• Small size (< 0.005 sq mm)
• Low Power (< 1.7mW)

PHY IP for LPDDR5 on Samsung 14nm

• Compliant with PHY standards
• Flexible Configuration
• Maximum data rates

2.5D Multi-Core Raster & Vector Graphics Processor for low-power SoCs with Microcontroller

• Programmable Shader engine with a VLIW instruction set
• Command list based DMAs to minimize CPU overhead
• Primitive Rasterizer

128-bit vector word length ARC VPX2 DSP IP with integrated hardware safety features for automotive

• Four-way VLIW combining scalar and vector operations
• 128-bit, 256-bit and 512-bit vector word lengths
• 8, 16, and 32-bit integer SIMD engines

CCSDS AR4JA LDPC Encoder and Decoder with code rates 1/2, 2/3, 4/5 and block sizes 1K, 4K, 16K

• Fully synchronous design, using single clock
• Fully synthesizable drop-in module for FPGAs
• Optimized for high performance and low resources

Very Low Area Fractional-N Frequency Synthesizer PLL

• Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
• Input & output frequency ranges greater than 1000:1

MIPI DSI-2 Transmit Controller v2.0

• Fully compliant to MIPI standard
• Small footprint
• Code validated with Spyglass

3.5 to 7 GHz Voltage controlled oscillator

• TSMC CMOS 55 nm
• VCO frequency tuning range from 3.5 GHz to 7 GHz
• Adjustable VCO core current

RISC-V CPU IP With ISO 26262 Full Compliance

• AndeStarâ„¢ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
• Floating point extensions
• Bit-manipulation extensions

UCIe Controller

• Low Latency controller for UCIe-based die-to-die connectivity
• Includes Die-to-Die Adapter layer and Protocol layer

High Performance HBM, HBM3 Memory Controller

• DRAM Supports
• High Performance
• Low Power Consumption

PCIe 6.0 SerDes PHY

• Complete SerDes subsystem solution with Rambus PCIe 6.0 controller core
• PIPE 6.0-compliant interface for Rambus PCI Express 6.0 Controller

Fractional-N PLL for Performance Computing in TSMC N5/N4

• Fractional multiplication with frequency up to 5GHz
• Low jitter (< 10ps RMS)
• Small size (< 0.003 sq mm)

eSPI & SPI Slave Controller w/FIFO

• Slave eSPI and standard Master SPI Modes

Chiplet Solution

PCI Express 6.0 PHY IP on N5

• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 6.0, encoding, backchannel initialization
• Supports PCIe Lane Margining at Receiver

LPDDR5X/5/4X PHY IP on TSMC N5

• Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
• Support for data rates up to 8533 Mbps

2.4 GHz transceiver for Bluetooth Low Energy

• Voltage supply: 1.3V down to 1V, with graceful degradation down to 0.9V
• Compliant with direct operation from 1.2V battery

TSMC CLN28HPC+ 28nm DDR 4/3 PHY - 3200Mbps

• Supports DDR4-3200, DDR3/L/U, LPDDR4/X and LPDDR3, simultaneously with one hard macro
• DFI 4.0 compliant

Bi-Directional LVDS with LVCMOS