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LPDDR5 IP - High performance and low power

• Support LPDDR5 up to 6400Mbps
• Support Channel equalization with 1-tap DFE

eUSB 2.0 PHY for TSMC N3A

• Compliant with eUSB2 specification rev 1.1
• Can be used in USB Host, Device, and Dual Role applications

1GHz to 3GHz, 6MHz to 100MHz Fractional-N Phase-Locked Loop

• TSMC SiGe BiCMOS 180nm
• Output clock frequency range from 6MHz to 100MHz
• Output LO frequency range from 1GHz to 3GHz

12-bit, 9.2 GSPS Analog-to-Digital Converter

• 12-bit Resolution
• 9.2 GSPS Sampling Rate
• 6 GHz Input Bandwidth

CH-6xx CryptoManager Hub

• NIST CAVP hardware classic cryptographic accelerators (AES, SHA-2, SHA-3, RSA, ECC), a NIST certified TRNG behind a highly efficient multi-channel DMA based AMBA interface.

FPGA Proven PCIe GEN6 Controller

• Supports up to x16 link width
• Support for Tx/Rx cut-through
• Supports 32 GT/s and 64 GT/s precoding

32 kHz RC low-drift oscillator in TSMC 22ULL

• High accuracy
• Low power
• Fast wake-up

MIPI D-PHY Receiver with PPI

• TSMC 12nm FFC Process
• Complies with the MIPI D-PHY interface Specification, version 1.2
• HS (High Speed) and LP (Low Power) mode supported

LDPC Encoder / Decoder

• Full hardware
• performance/gatecount
• configurable generator matrix

5 GHz 250 fs jitter Phase Locked Loop IP Block

• Input Frequency: ~100MHz
• Output Frequency: 5 GHz
• RMS Jitter: <250 fs
• Supply Voltages: 0.8 V (Core), 1.8V (IO)

MIPI C-PHY v2.0 D-PHY v2.1 RX for GF 12LP+

• Compliant with the MIPI D-PHY specification, v2.1
• 4 Lanes in D-PHY mode up to 6.5Gb/s per lane

GDDR7 Memory PHY for TSMC N3P

• JEDEC JESD250C standard compliant
• Advanced process node
• East-West and North-South orientation

Smart Network-on-Chip (NoC) IP

• Smart NoC automation
• Topology generation with minimum wire length
• Scripting-driven regular topology creation

Post-quantum secure root of trust subsystem

• Secure key management features
• Configurable power-side channel countermeasures.
• Configurable fault-tolerance countermeasures.

Clock Attack Monitor TSMC

• Input frequency: Up to 100 MHz
• Relative frequency measurement capability
• Relative frequency measurement resolution (frel): 10kHz

1.8V & 3.3V Radiation Hardened GPIO with Optimized LDO

• 2mA, 4mA, 8mA and 16mA drive strengths
• Pairs with optimized LDO (3.3V only)
• Full-speed output enable

Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more

• Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
• Extremely low jitter suitable for Enterprise SerDes applications

Passive/active NFC transceiver

• TSMC 180 nm 6 metals generic process without analog options
• Differential antenna interfaces with dedicated external capacitors for antenna impedance matching

TSMC GF Intel Samsung Deskew Frequency Synthesizer PLL

Ultra low-power crystal-based 32 kHz oscillator designed in TSMC 12FFC+

• Compatible with 4 pF to 12.5 pF crystals
• Tolerate no load capacitance on the board to minimize the BoM
• FOK signal indicating when the clock signal is ready

Automotive MIPI A-PHY Sink IP (2-Lane)

• Compliant with MIPI A-PHY specification version 1.0
• Support Gear-2 up to 4Gbps

GDDR7 Memory PHY for TSMC N3P

• JEDEC JESD250C standard compliant
• Advanced process node
• East-West and North-South orientation

LPDDR5/4/4X PHY in TSMC (16nm, 12nm, N7, N6, N5)

DXTP GPU - Advanced graphics and compute acceleration for power constrained devices

• The ideal platform for edge compute
• Pixel-perfect graphics
• Everything developers need