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Low Power Bluetooth Low Energy Version 5 PHY

• Modem with Integrated 2.4GHz RF Radio
• Compliant with Bluetooth 5 Low Energy Specification
• 1 Mbps/2 Mbps Data Rates

Multi-Link Multi-Protocol SerDes 10Gbps in GF 28SLP

• Configurable parallel data widths of 8 / 16 / 32 –bit
• Input reference 125MHz to support 2.5/5/10G data rates & 100MHz to support 2.5/5/8/16G data rates

Linear Li-Ion Battery Charger

• Programmable charging current up to 1.1A
• SilTerra 0.18um

UFS Host 3.0 Prototyping Kit (HDK )Total IP in a Box

• UFS 3.0 Host and Device configurations available
• Complete UFS 3.0 hardware implementation
• Interop-proven UniPro 1.8 link layer

Fractional-N RF PLL

• TSMC 40nm CMOS
• 6.0GHz-to-9.7GHz Buffered VCO PLL Output Coverage
• Scalable Power Consumption

ASIL D Ready Security Enhancement Package for EV6x Embedded Vision Processors

• Optimized for high frame-rate and video resolution embedded vision applications
• Integrates 32-bit scalar core, 512-bit vector DSP, and optional CNN engine

Image Processor

• High Performance
• Low Power Consumption
• Seamless Software Integration

VESA VDC-M Encoder

• VESA Display Compression-M (VDC-M) 1.1 compliant
• Supports all VDC-M encoding mechanisms

UFS 3.0 Host Controller with AES Encryption

• UFS 3.0 Host and Device configurations available
• Complete UFS 3.0 hardware implementation
• Interop-proven UniPro 1.8 link layer

6MHz ±1% PVT 1.8V Low Power Oscillator in Silterra 0.18um

• Silterra 0.18um
• 6MHz +/- 1% after trimming
• Supply 1.8V +/- 10%
• Low power (17μA)

8Gbps PCIe3.0 PHY

• Single Lane and Quad Lane
• Samsung 28LPP process

12-Bit Video DAC with Low Pass Filter

• 55nm GlobalFoundries LPe, 6 Metals
• 3.3V and 1.2V Supplies
• Single VDAC

DDR5 Controller and PHY

• Silicon-proven DRAM interoperability at 4400 MT/s
• Lowest-latency DDR controller and PHY IP

IEEE 802.11ah MAC/PHY

• 1 MHz and 2 MHz channel width
• S1G_1M, S1G_SHORT PPDU
• Mandatory MAC including TXOP, RID, SST, TWT, AID,…, RAW

Fractional-N Frequency Synthesizer PLL (7nm - 180nm)

• 1MHz up to 1.6GHz input frequency range
• 1MHz up to 3.6GHz output frequency range
• 24 bit fractional resolution

ARC Secure IP Subsystem (SEM)

• Pre-verified subsystem protects against malicious attacks targeting high value applications
• Integrated, ARC SEM Security Processor protects against side-channel attacks

Arm Cortex-M35P

• Tamper-resistant Cortex-M processor with optional software isolation using TrustZone for Armv8-M

Convolutional Accelerator for Convolutional Neural Networks (CNN)

XpressCCIX Controller for PCIe with Support for CCIX ESM

• Track record of silicon proven PCIe 4.0 designs guarantees first-time silicon success

Ultra-Low Power 32kHz Xtal Oscillator

• 65nm TSMC Logic LP Process, 4 Metals Used (No Analog Options) with Deep-Nwell
• Ultra-Low Power Crystal Oscillator

Automotive Ethernet MAC IP

• IEEE 802.3 compliant, UNH tested and ISO 26262 ASIL-B qualified
• Enhanced active functional safety features

DesignWare MIPI D-PHY IP for TSMC 7FF

• Compliant with MIPI D-Phy Interface Specification, rev. 1.0
• Fully integrated hardmacro
• Up to 1Gbps per lane. Up to 4 Data lanes

JESD204B Controller IP core

• Standard version: JESD204B.01, January 2012
• Versions Available: Transmitter / Receiver
• Silicon Agnostic: Targets ASIC, ASSP, FPGA

RISC-V processor

• RV32IM ISA
• 1.9 DMIPS/MHz
• 100 MHz