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Process Node	4nm 5nm 7nm 8nm 10nm 12nm 16nm 20nm 22nm 28nm 40nm 55nm 65nm 90nm 130nm 150nm 180nm 250nm
Foundry	GLOBALFOUNDRIES HHGrace IBM LFoundry Renesas Samsung SilTerra SMIC Tower TSMC UMC X-FAB

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APEX 20KC APEX 20KE APEX II Arria Arria 10 Arria 10 GT Arria 10 SoC Arria 10 SX Arria GX Arria GX Arria II Arria II GX Arria II GZ Arria V Arria V GT Arria V GX Arria V GZ Arria V SoC Arria V ST Arria V SX Cyclone Cyclone 10 GX Cyclone 10 LP Cyclone II Cyclone III Cyclone III LS Cyclone IV Cyclone IV E Cyclone IV GX Cyclone Series Cyclone V Cyclone V E Cyclone V GT Cyclone V GX Cyclone V SE Cyclone V SoC Cyclone V ST Cyclone V SX eASIC N2X eASIC N2XT eASIC N3X eASIC N3XS HardCopy HardCopy II HardCopy III HardCopy IV E HardCopy IV GX MAX 10 MAX 10 DF MAX II MAX V Stratix Stratix 10 Stratix 10 GX Stratix 10 MX Stratix 10 SX Stratix 10 TX Stratix GX Stratix II Stratix II GX Stratix III Stratix III E Stratix IV Stratix IV E Stratix IV GT Stratix IV GX Stratix V Stratix V E Stratix V GS Stratix V GT Stratix V GX	Artix-7 Artix-7 -2L Kintex UltraScale Kintex UltraScale+ Kintex-7 Kintex-7 -2L Spartan-3 Spartan-3 XA Spartan-3A Spartan-3A DSP Spartan-3A DSP XA Spartan-3A XA Spartan-3AN Spartan-3E Spartan-3E XA Spartan-6 Spartan-6 -1L Spartan-6 HXT Spartan-6 LX Spartan-6 LXT Spartan-6 XA Spartan-6 XC Spartan-7 Spartan-II Spartan-IIE UltraScale UltraScale+ Virtex UltraScale Virtex UltraScale+ Virtex-4 Virtex-4 FX Virtex-4 LX Virtex-4 SX Virtex-4 XA Virtex-5 Virtex-5 FX Virtex-5 FXT Virtex-5 LX Virtex-5 LXT Virtex-5 SX Virtex-5 SXT Virtex-5 TXT Virtex-6 Virtex-6 -1L Virtex-6 CXT Virtex-6 HXT Virtex-6 LX Virtex-6 LXT Virtex-6 SXT Virtex-6 XC Virtex-7 Virtex-7 -2G Virtex-7 -2L Virtex-7 HT Virtex-7 XT Virtex-7T Virtex-E Virtex-II Virtex-II Pro Zynq UltraScale+ MPSoC Zynq-7000	ispClock ispMACH 4000 LatticeEC/ECP LatticeECP2 LatticeECP2M LatticeECP3 LatticeECP5 LatticeSC LatticeSCM LatticeXP LatticeXP2 MachXO MachXO2 MachXO3 Platform Manager Power Manager II	Axcelerator eX Fusion IGLOO IGLOO nano IGLOO PLUS IGLOO2 MX Polarfire ProASIC3 ProASIC3 nano ProASIC3E ProASIC3L ProASICPLUS RT ProASIC3 RTAX-S/SL/DSP RTG4 RTSX-SU SmartFusion SmartFusion2 SX-A

New Silicon IP

• 25 to 1750 MHz quadrature mixer

  • TSMC CMOS 55 nm
  • Operating frequency range from 25 to 1750 MHz
  • Noise figure 8.2 dB
  
   
  
  

• PCIE 5.0 PHY in Samsung 10/8LPP, SMIC 14SFE/SF+, and TSMC 12FFC

  • Support 32Gbps serial data transmission rate
  • Utilizes 8-bit, 16-bit or 32-bit parallel interface to transmit and receive data
  
   
  
  

• SERDES IP 16Gbps per channel

  • 8 channel SERDES (TXRX), operating at data rates from 1.5Gbps to 16Gbps per channel
  
   
  
  

• FPGA Evaluation Platform

  • For Codasip Application Processor RISC-V cores
  • Including AXI or AHB interconnect and PeripheralsAXI or AHB interconnect
  
   
  
  

• AI accelerator - 4.5K, 9K, or 18K INT8 MACs

  • Performance efficient 18 TOPS/Watt
  • Scalable performance from 18K MACS
  • Capable of processing HD images on chip
  
   
  
  

• Nano power DC-DC converter in GF 22FDX with ultra-low quiescent current and high efficiency at light load

  • Ultra-low quiescent current (300 nA) to ensure minimum current consumption in deep sleep / hibernation mode
  
   
  
  

• Automotive ASIL B Compliant tRoot Hardware Secure Module IP

  • Safety mechanisms for ASIL B compliance for random faults and ASIL D compliance for systematics
  
   
  
  

• 12-bit 5MS/s Low Latency Voltage DAC

  • 16nm TSMC FFC Process, 7 Metals Used
  • 1.8V, and 0.8V Supplies
  • 12 Bit Voltage DAC resolution
  
   
  
  

• ARINC 818 Transmitter & Receiver

  • Compliant to ARINC818-2 Specification.
  • Data rate up to 4.25 Gbps and Low Latency.
  
   
  
  

• PCIe Controller for USB4 Hosts and Devices supporting PCIe Tunneling, with optional built-in DMA and configurable AMBA® AXI Interconnect

  • Designed to the USB4 Specification v1.0
  • Follows PCIe 1.0 protocol, but can operate at any compatible speed
  • Supports the PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
  
   
  
  

• DVB-GSE Ethernet Tunnel IP Core

  • GSE encapsulation of Ethernet frames
  • Designed for high throughput and low latency
  
   
  
  

• 300mA buck converter - TSMC 0.18um BCD

  • 5V Input Voltage
  • 1.2/1.8V Output Voltage options
  • 300mA maximum current load
  
   
  
  

Top Silicon IP

• 1

  AI accelerator - 2.25K, 4.5K, or 9K INT8 MACs

  • Performance efficient 18 TOPS/Watt
  • Scalable performance from 2-9K MACS
  • Capable of processing HD images on chip
  
   
  
  
• 2

  Gigabit Ethernet PHY

  • Comply with IEEE 802.3ab, 802.3u, and 802.3
  • Support IEEE 802.3az Energy Efficient Ethernet
  
   
  
  
• 3

  FPGA Evaluation Platforms for RISC-V Processor Cores

  • Greatly simplifies the evaluation of a Codasip embedded RISC-V core by providing a ready-to-go platform including common peripherals, Xilinx memory and software examples.
  
   
  
  

• 4

  Ethernet Subsystem 10G/25G

  • Flexible
  • 5G Ready
  • Ease-to-use and Reliable
  
   
  
  
• 5

  PCIe Controller for USB4 Hosts and Devices, supporting PCIe Tunneling

  • Designed to the USB4 Specification v1.0
  • Follows PCIe 1.0 protocol, but can operate at any compatible speed
  
   
  
  
• 6

  Automotive MIPI A-PHY Source IP - 1-Lane

  • Compliant with MIPI A-PHY specification version 1.0
  • Support Gear-2 up to 4Gbps
  • Support data bus width: 20-bit parallel interface
  
   
  
  

• 7

  Asynchronous Network on Chip IP

  • High performance interconnects, Ultra-low-latency and Deep pipelining
  
   
  
  
• 8

  Complete Neural Processor for Edge AI

  • Designed for Low-Power Neural Network Processing
  • Flexible Training Methods
  • Scalable Neuron Fabric
  
   
  
  
• 9

  5G/802.11ax MIMO Analog Front-End on TSMC 12nm FFC

  • TSMC 12nm FFC Process,
  • Customizable AFE
  • 1.8V and 0.9V Supplies
  
   
  
  

• 10

  32G Multi-protocol SerDes PHY

  • Multi-protocol PHYs supporting data rate in the range of 2.5 Gbps – 32 Gbps
  • Available in GLOBALFOUNDRIES 22FDX® process node
  
   
  
  
• 11

  Viterbi Decoder

  • Hard or soft decoder with configurable soft bit widths
  • Parameterisable generator polynomials
  • Parameterisable code Constraint length
  
   
  
  
• 12

  Powerline (PLC), Wireline, G.hn, G,Fast, Analog Front-End (AFE) ultra-efficient Area and Power

  • High Performance.
  • Low Power
  • Low Area
  
   
  
  

¹ Top Silicon IP Over the Last Two Weeks (Last update: May. 2)

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