D&R Headline News (Last 14 Days)

Headlines for Friday Jul. 01, 2022

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Sondrel appoints Gareth Jones as VP ASIC

Sondrel Limited has recruited industry veteran, Gareth Jones to head up its turnkey ASIC services. He joins from TSMC where he was director of Marketing for EMEA and he has over 25 years of experience in both ASIC and foundry services.

• Accenture Completes Acquisition of XtremeEDA to Expand Silicon Design Capabilities in Canada and US

Headlines for Thursday Jun. 30, 2022

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Xiphera's first financing round successfully completed

Xiphera's first financing round was led by anchor investor Gorilla Capital, which was joined by two other institutional investors — Korpun Seed Ltd from SijoittajaPRO Corporate Finance and Ääkköset Oy — as the three main investors.

• Breker Verification Systems Joins RISC-V International as a Strategic Member to Drive Cache Coherency and SoC Integration Verification Methodologies
• 2022 a Focus for 12-inch Capacity Expansion, 20% Annual Growth Expected in Mature Process Capacity, Says TrendForce
• Alphacore Joins Forces with Quantum Leap Solutions to Bring World-Class Design IP to the North American Commercial Market
• The Role of Hardware Root of Trust in Edge Devices
• New S2C Multi-FPGA Prototyping Software Eases the Pain
• Intel Foundry Services Forms Alliance to Enable Design in the Cloud
• ETSI and MIPI Alliance Announce Incorporation of MIPI I3C Basic into ETSI Smart Secure Platform
• Top Five MPU Suppliers Expand Share of Sales to 86% in 2021
• New Cadence Xcelium Apps Accelerate Simulation-Based Verification for Automotive, Mobile and Hyperscale Designs
• Samsung Begins Chip Production Using 3nm Process Technology With GAA Architecture
• Truechip Adds USB 4 Hub Model & USB 4 Retimer Model to its Verification IP Portfolio

Headlines for Wednesday Jun. 29, 2022

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EnSilica chassis control ASIC for premium automotive brand enters mass production

EnSilica (LON: ENSI), a leading chip maker of mixed signal ASICs (Application Specific Integrated Circuits), has announced the development of a custom chassis-control ASIC, which has entered mass production, and will appear in vehicles later this year.

• Vidatronic Announces Power Management IP Now Certified on Globalfoundries' 22FDX® Platform for IoT Applications
• Synopsys and Arm Strengthen Partnership to Advance Next-Gen Mobile SoCs for Arm's Total Compute Solutions
• Arm Total Compute Solutions redefine visual experiences and supercharge mobile gaming
• Cadence and Intel Foundry Services Collaborate to Accelerate Innovation with Scalable and Proven Cadence Cloud Solutions
• Cadence Expands Collaboration with Arm to Accelerate Mobile Device Silicon Success
• Weebit Nano tapes out ReRAM demo chip to SkyWater foundry

Headlines for Tuesday Jun. 28, 2022

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UMC, eMemory, and PUFsecurity Announce Successful Silicon-Proven Secure Embedded Flash IP

eMemory and its subsidiary PUFsecurity, and United Microelectronics Corporation announced today the successful silicon qualification of the world’s first PUF (Physical Unclonable Function)-based secure embedded flash solution.

• Enhanced Serial Peripheral Interface (eSPI) Master/Slave Controller
• Vayyar Selects proteanTecs to Advance Vehicle Safety with Predictive Analytics
• Flex Logix Hires Barrie Mullins as Vice President of Product Management
• Synaptics Selects Allegro DVT's VVC Compliance Streams
• Accenture Announces Intent to Acquire XtremeEDA to Expand Silicon Design Capabilities in Canada and US
• SiFive Expands Global Operations, Opens UK R&D Center in Cambridge
• New startup MachineWare enables ultra-fast RISC-V simulation
• Meet Axiomise's Ashish Darbari at DAC to Learn about Benefits of Formal Verification

Headlines for Monday Jun. 27, 2022

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Flex Logix and CEVA Announce First Working Silicon of a DSP with Embedded FPGA to Allow a Flexible/Changeable ISA

Enabling flexible and changeable instruction sets to meet demanding and changing processing workloads, the ASIC, known as SOC2, was designed and taped out in a TSMC 16 nm technology by Bar-Ilan University SoC Lab, as part of the HiPer Consortium, backed by the Israeli Innovation Authority (IIA).

• sureCore's ultra-low memory technologies enable designers to create the reality of the metaverse
• IAR Systems enable Visual Studio Code extensions to meet developer demands
• TSMC Japan 3DIC R&D Center Completes Clean Room Construction in AIST Tsukuba Center
• Ansys Multiphysics Solutions Achieve Certification for TSMC's N3E and N4P Process Technologies
• Ansys and TSMC Collaborate to Deliver Multiphysics Design Methodology for Wireless Chips
• GbE (10/100/1000 Base-T) PHY IP licensed by 3 different customers in Q2 alone for Worldwide Use

Headlines for Thursday Jun. 23, 2022

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CFX announces commercial availability of anti-fuse OTP technology on 90nm CIS process

CFX, the one stop shop of embedded flash memory IP and stand alone flash memory IC provider announced today commercial availability of anti-fuse OTP technology on 90nm CIS process.

• IPrium releases 4-channel ATSC 8VSB Modulator
• Pulsic Enhances Unity Chip Planning Technology with Incremental Floor-planning Capability to Speed IP block Placement, Planning
• TSMC Creates Design Options for New 3nm Node
• Xiphera receives Business Finland's Young Innovative Company funding
• Weebit Nano to publicly demonstrate its ReRAM IP module for the first time
• Synopsys Completes Acquisition of WhiteHat Security
• GlobalFoundries Celebrates New Singapore Fab with Arrival of First Tool
• Brite Launches High-Precision 16 bit SAR ADC
• Tortuga Logic Rebrands as Cycuity as It Addresses Evolving Needs in Product Security

Headlines for Wednesday Jun. 22, 2022

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CEVA Extends its RivieraWaves UWB IP to Support CCC's Digital Key 3.0 Standard for Keyless Access to Vehicles

CEVA-RivieraWaves™ UWB platform IP for IEEE 802.15.4z enhanced with an optimized software MAC layer for the Car Connectivity Consortium® Digital Key 3.0, already in design with tier 1 automotive semiconductor

• M31 Technology has Developed and Validated the Ultra-Low Power 12nm PCIe 5.0 High-Speed Interface IP
• XtremeEDA to enable IoT security deployment with Crypto Quantique's solution using Codasip's RISC-V processor
• PCI-SIG® Announces PCI Express® 7.0 Specification to Reach 128 GT/s
• Codasip adds Veridify secure boot to RISC-V processors
• Intento Design Secures Third Round of Investment to Accelerate Its Commercial Deployment
• MosChip Technologies Appoints Semiconductor Industry Veteran, DVR Murthy As "Vice President of Strategic Initiatives" to Implement and Execute Expanded Solution Offerings

Headlines for Tuesday Jun. 21, 2022

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Avery Design Systems PCI Express VIP Enables eTopus SerDes IP and Next-Generation ASIC and Chiplet applications to Achieve Compliance and High-Speed Connectivity

Avery Design Systems, a leader in functional verification solutions, today announced it has been chosen by eTopus as its verification IP solution partner for eTopus PCIe Gen 1-6 and 800G/400G Ethernet solutions and 112G SerDes IP for next-generation ASIC and Chiplet applications.

• Expedera Expands Global Reach with New Regional Design Centers and Chinese Langauge Website
• Cadence Achieves PCIe 5.0 Specification Compliance for PHY and Controller IP in TSMC Advanced Technologies
• Codasip L31 customizable RISC-V core is an Embedded World Best in Show
• Imagination launches IMG RTXM-2200 - its first real-time embedded RISC-V CPU
• OpenHW Group Announces RISC-V-based CORE-V MCU Development Kit for IoT Built with Open-Source Hardware & Software
• CV32E40P Core From OpenHW Group Sets the RISC-V Quality Standard For Open-Source Hardware IP
• Dolphin Design wins an Embedded Award for Tiny Raptor, its Energy-Efficient Neural Network AI Accelerator
• RISC-V Announces First New Specifications of 2022, Adding to 16 Ratified in 2021
• OPENEDGES to Demonstrate Latest NPU IP, ENLIGHT at CVPR 2022
• Codasip Studio Mac extends potential to design for differentiation with RISC-V
• Cadence Announces $100 Million Accelerated Share Repurchase Agreement
• SiFive Enhances Popular X280 Processor IP to Meet Accelerated Demand for Vector Processing

Headlines for Monday Jun. 20, 2022

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World's First AV1 Decoder Silicon IP with support for 12-bit pixel size and 4:4:4 Chroma Sub-Sampling Released by Allegro DVT

Allegro DVT, the leading provider of video processing silicon IPs and video compliance streams, has announced that its D310 AV1 decoder silicon IP now supports 12-bit sample size and 4:4:4 chroma sub-sampling.

• Fraunhofer IPMS develops CANsec Controller IP-Core CAN-SEC
• World's first end-to-end integration of ZKP with FPGAs.
• Samsung Ventures invests in Israeli AI systems and semiconductor company NeuReality
• Complete UFS 3.1 Controller solution (Analog / Digital IP Cores) licensed to China's leading Smartphone Company
• VisualSim Antenna System Designer enables simulation of Antenna and Communication Systems
• Huawei and Nordic cellular IoT licensing deal takes a big step towards industry-wide component-level licensing

Headlines for Friday Jun. 17, 2022

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TSMC FINFLEX™, N2 Process Innovations Debut at 2022 North American Technology Symposium

TSMC today showcased the newest innovations in its advanced logic, specialty, and 3D IC technologies at the Company’s 2022 North America Technology Symposium, with the next-generation leading-edge N2 process powered by nanosheet transistors and the unique FINFLEX™ technology for the N3 and N3E processes making their debut.

• Cadence RFIC Solutions Support TSMC N6RF Design Reference Flow
• Synopsys Boosts 5G SoC Development Productivity with New RF Design Flow for TSMC N6RF Process
• Embedded World fair: Menta will unveil an unprecedented collaboration with Everspin Technologies

Headlines for Thursday Jun. 16, 2022

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QuickLogic and eTopus Announce Disaggregated, Flexible eFPGA Chiplet Template

QuickLogic Corporation (NASDAQ: QUIK), a developer of ultra-low power multi-core voice-enabled SoCs, embedded FPGA IP, and Endpoint AI solutions, and eTopus, a leader in high speed, low latency, low power connectivity IP, today announced the industry’s first disaggregated eFPGA-enabled chiplet template solution.

• OpenFive Joins Universal Chiplet Interconnect Express (UCIe) Consortium
• Siemens extends support of multiple IC design solutions for TSMC's latest processes
• Cadence Design IP portfolio in TSMC's N5 Process Gains Broad Adoption Among Leading Semiconductor and System Companies
• SmartDV Charts Course Toward Chiplets, Joins Universal Chiplet Interconnect Express (UCIe)
• CAST and Fraunhofer IPMS Mark 20-Year Partnership with Product of the Year Win
• Renesas Develops Circuit Technologies for 22-nm Embedded STT-MRAM with Faster Read and Write Performance for MCUs in IoT Applications
• Avery Design Systems Announces Verification Support for New UCIe standard, Accelerating Adoption of Chiplet Interconnect Protocol
• Alchip Technologies Offers 3nm ASIC Design Services
• Silicon Topology Joins TSMC Design Center Alliance (DCA)