32-bit RISC-V embedded processor with TUV SUD ISO 26262 ASIL B certification
ESL Design Articles
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Introduction to and Regression Test for OCP SystemC Channel Models (Sep. 04, 2007)
Using OCP, IP designers can make their cores independent of some specific bus protocols, and hence the IP cores will be suitable for any particular design implementation. This makes it easier to reuse OCP-compliant cores across multiple SOC designs. Traditionally designers have to support different bus protocols by modifying a core's interface, the verification suite, the test bench, the documentation, and all other interface-related design issues of the core.
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Using an open debug interconnect model to simplify embedded systems design (Aug. 30, 2007)
An open debug interconnect model is proposed for understanding debugger component interactions.
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Distributed Software Behaviour Analysis Through the MPSoC Design Flow (Aug. 27, 2007)
The complexity of developing Systems-on-Chip (Soc) is increasing continuously, but the productivity of hardware and software developers is not growing at a comparable pace. As a consequence, the conception of a new SoC can take a few years and software can’t wait its availability.
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A New Methodology for Hardware Software Co-verification (Jul. 30, 2007)
Traditional methods of hardware software co-verification use either the industry standard accelerators/emulators or the instruction set simulators. Both the methodologies are well proven and are well established in SOC verification environment. The design, development and validation of device drivers require these tools and software and it would be an expensive proposition for IP developers.
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Transaction Level Model of the USB On-The-Go controller IP core (Jul. 23, 2007)
The paper describes a transaction level model of the serial bus controller compliant to USB On-The-Go specification [1]. The model has been developed as an abstraction of an existing IP core, written in VHDL. The possible use in the development or testing of a software driver was addressed too.
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Commentary: SystemVerilog enables design with verification (Jun. 28, 2007)
The SystemVerilog language standard is one of the hottest topics in EDA today, and with good reason.
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Video codecs in SoCs using OCP-based programmable accelerator design (Apr. 30, 2007)
Flexibility is increasingly necessary when supporting multiple standards, such as the VC-1 and H.264 video codecs within a single SoC. This flexibility can be achieved by having programmable state machines instead of hardwired state machines.
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Transaction Recording, Modeling and Extensions for SystemVerilog (Apr. 16, 2007)
This paper discusses ways to improve the adoption rate by improving the usability and simplifying the modeling concepts. Using SystemVerilog we demonstrate a simplified PLI interface for recording transactions and we extend previous language standard changes to improve automation.
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A system-level verification flow for EDA (Mar. 19, 2007)
The EDA industry continues to innovate and develop cutting-edge tools for the design and verification of hardware. But it has not yet found a way to accelerate growth within hardware/ software development or to capitalize on the interest around what Cadence calls enterprise system-level (ESL) solutions.
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A Simple New Approach to Hardware Software Co-Verification (Mar. 05, 2007)
Coverage-driven verification (CDV) has generated remarkable interest in recent years. Because of its enormously comprehensive capabilities, more and more verification teams are now relying on the CDV approach.
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Demystifying ESL for embedded systems designs (Mar. 01, 2007)
While the definitions of ESL may vary, the end result should be the same, namely letting system developers analyze their designs at a higher level of abstraction.
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Use ESL synthesis techniques to replace dedicated DSPs with FPGAs (Mar. 01, 2007)
If your application isn't the most compute intensive, you may find that using an FPGA as a replacement is a good idea.
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Fast Virtual Prototyping for early software design and verification (Feb. 26, 2007)
This paper describes a simplified and novel approach for fast and easy virtual prototyping which provides a fully functional and accurate platform for the embedded software developer. This platform enables the software developer to execute the same binary image on the virtual platform as he would on the real hardware. The virtual platform, thus developed, can also be used for meaningful development of newer software features and upgrades, and will carry a lot of value for software development.
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System simulation speeds application development (Feb. 26, 2007)
The wide range of different types and models of mobile phones can be a significant problem for developers of software. While the majority of phones are based on the ARM processor architecture, there are many different implementations with processor cores from the ARM9 and ARM11 families, and different ranges of peripherals from suppliers such as Texas Instruments, Qualcomm or Atmel.
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Accelerated IP Model Development (Feb. 22, 2007)
IP-based SOC designs are increasingly dependent upon ESL methodologies to balance the constantly increasing pressure on both schedule and design complexity. In order to meet these demands, system models need to be generated rapidly and delivered to the teams developing the architecture, coding the implementation and validating the software. This paper will discuss a method for accelerating the development and validation of these complex system models.
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Plan your verification with SystemVerilog (Feb. 19, 2007)
As verification engineers move to more-sophisticated techniques for system-on-chip (SoC) designs, their planning process is evolving as well. Traditional test-based planning is being supplanted by more sophisticated verification plans tracking coverage and assertions. One factor in this change is the widespread adoption of SystemVerilog, which supports the specification of functional coverage points, assertions and testbench constraints.
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Programmable accelerators: hardware performance with software flexibility (Feb. 01, 2007)
Programmable accelerators combine the performance of custom hardware with the flexibility of software--and they are surprisingly easy to design. This article shows how to specify, profile, and debug a programmable accelerator, all in a matter of weeks.
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Defining the TLM-to-RTL Design Flow (Jan. 18, 2007)
As System-on-Chip (SoC) designs grow ever larger, design and verification flows are changing. A rich mix of features, increased software content, high intellectual property (IP) use and submicron implementation technology have semiconductor and system companies searching for new electronic system level (ESL)-based design flows.
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How NXP uses Spirit/ESL-based IP ''Yellow Pages'' to speed System-on-Chip design time (Dec. 07, 2006)
You can either spend a month hand-crafting the last few hundred square microns of silicon out of a system-on-chip (SoC) design or you can put your product on the market one month quicker.
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''Enterprise'' System Level (ESL) Verification -- PART II (Dec. 04, 2006)
Hardware and embedded software development at the system-level will only require more verification cycles and proven methodologies to adhere to the specification to expose system-level errors and manage overall project risk
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We Need ''Enterprise'' System-Level Solutions (Nov. 23, 2006)
To close the gaps in systems development across distributed design and verification teams it will become necessary to plan, design, and verify embedded software closer in-line with the way we currently design and verify hardware.
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Fit the hardware to the algorithm with SystemC models (Oct. 12, 2006)
Learn how to model DSP algorithms in SystemC without being a SystemC expert. These models facilitate hardware/software partitioning, and allow you to consider communication and memory architectures when designing your algorithm. These models also ease sof
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Getting Practical with ESL Design Methodologies (Sep. 21, 2006)
ESL is emerging as viable – indeed necessary – part of the SoC design process. The viability is being driven by the emergence and adoption of industry-wide standards.
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SystemVerilog Reference Verification Methodology: VMM Adoption (Sep. 04, 2006)
This article focuses on ways to adopt the VMM methodology and deploy it quickly throughout an entire SoC project.
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Complex DSP system modeling made easy (Aug. 31, 2006)
Polymodeling provides a single specification that can be used throughout the process of algorithmic exploration, fixed-point optimization, and implementation verification. Learn how this approach can save you time and effort
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How to use UML in your SoC hardware/software design: Part 1 (Jul. 17, 2006)
From determining the hardware/software partition to meeting performance and cost objectives, the job of building systems on a chip has never been easy, and with ever-increasing demand for more functionality packed into smaller spaces consuming less power,
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Legacy RTL brought into system-level flow (Jun. 27, 2006)
Designers might hesitate to use ESL because of legacy RTL intellectual-property libraries that represent thousands of man-years of invested time. But legacy RTL IP can be the basis for new designs that leverage ESL methodologies.
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Cycle Accuracy Analysis and Performance Measurements of a SystemC model (Jun. 19, 2006)
The scope of this paper is to highlight the methodology adopted to address cycle accuracy and performance measurement of a SystemC model. These are initial steps, which provide directions to the measurement of cycle accuracy.
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A Case Study in Rule-Based Modeling (Jun. 15, 2006)
We present a case study in employing rule-based high-level synthesis to implement a parameterizable general purpose processor. We contrast a generic implementation in Bluespec SystemVerilog to reference implementations in VHDL and SystemVerilog, and discu
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SystemVerilog reference verification methodology: ESL (Jun. 12, 2006)
This is the third in a series of four articles outlining a reference verification methodology that covers both RTL and system-level requirements. This methodology is enabled by the SystemVerilog hardware design and verification language standard and is do