In this column, I'm continuing a mini-series on the development of the Serializer Deserializer (SerDes or SERDES) functions that are embedded into today's FPGAs. In my previous post on this topic, I discussed some of the current features of SerDes technology in FPGAs. Today, we continue the discussion and review some of the key challenges facing SerDes technology in FPGAs. (If you are new to SerDes technology, a good resource to use to review the basics is a DesignCon 2004 paper from Dave Lewis, titled "SerDes Architectures and Applications.")
Adding specialized features
Once the solid foundation features have been created, the FPGA architecture can layer more specialized features on top to cover the plethora of standard-specific requirements. In many cases, these features can be created to cover multiple standards; as FPGA manufacturers have become increasingly involved in standards creation, it has been possible to cover more standards with a smaller number of special blocks. Two good examples are Signal Conditioning and On-Die Instrumentation.
Signal conditioning is the process of improving a signal's characteristics as it is transmitted over a "lossy" transmission channel. Channels are never perfect and usually include attenuation, reflections, radiation, and coupling that degrades the incident signal. The figure below illustrates some of the real-world connectors, backplanes, and I/O (input/output) cards that can degrade an incident signal.
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