Industry Expert Blogs

Hyperscale data centers are rapidly evolving to accommodate a wide range of high-bandwidth, low-latency applications, from artificial intelligence (AI) and high-performance computing (HPC) to telecommunications and streaming 4K video. These applications are enabled by a new generation of multi-die systems, AI accelerators, and machine learning (ML) training sets that require ever-higher transfer speeds. To meet this demand, Ethernet has scaled from 51Tb/s to 100Tb/s, while switch transfer rates have increased from 51Tb/s to 100Tb/s.

Higher data transfer rates have prompted hyperscale data centers worldwide to deploy end-to-end networking infrastructure built with interface IP that uses pulse amplitude modulation 4-level (PAM-4) signaling techniques. Compared to non-return-to-zero (NRZ) signaling, PAM-4 enables higher bit rates at half the baud rate. Although PAM-4 signaling increases design complexity with added crosstalk and non-linearity, PAM-4 is now the de-facto signaling modulation for interface IP—including 112G Ethernet PHYs—in hyperscale data centers and the broader HPC system-on-chip (SoC) market.

Read on to learn how to optimize implementation of 112G Ethernet PHY IP for HPC SoCs. Gain insights from companies that are leveraging 112G Ethernet PHY IP to design many different types of high-bandwidth networking devices and infrastructure, including AI accelerators, servers, and network interface cards (NICs), as well as networking and interconnect fabric SoCs, optical modules, storage devices, and retimers.

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