The synthesizable IEEE1394b Link Layer Controller Core, FireLink®, is based on the Link Layer Controller that has been used for several years in the FireSpy® analyzers produced by DapTechnology. The code is written in VHDL and reference designs are currently available for Xilinx and soon for Altera FPGAs. DapTechnology offers two packages, i.e. Basic and Extended with differnet features and functions.
Currently, the LLC provides the control for transmitting and receiving 1394 packet, including asynchronous packets, isochronous packets and Phy packets, at speeds up to 800Mb/s. Future enhancements will support S1600 and S3200 speeds. However, support for these speeds is pending the final PHY/Link interface standardization.
As a special option, the FireLink® LLC offers Firmware Support for the AS5643 (Mil1394) protocol. While current implementations require significant host SW support the FireLink can support this layer with significantly better timing as well as reduced host resource utilization. Typical examples of applications in aerospace & defense for the FireLink® would include command & control systems for space-based vehicles, missile platforms, and fighter aircraft, as well as its implementation in avionics & IFE platforms for business and commercial aircraft.
Features
- Host Bus Interface
- Generic: A generic 32-bit synchronous host bus.
- OPB: A 32-bit synchronous bus used in Xilinx FPGAs for their MicroBlaze and PowerPC processors.
- Avalon: A 32-bit synchronous bus used in Altera FPGAs for their NIOS processor.
- The Basic version is implemented as a slave-only bus interface while the Extended version, however, will utilize a DMA engine which will access the bus as a Master.
- Control Status
- Both versions have a number of registers that can be written and or read. They are used to control the Link Layer Controller and to check its status. For the Extended version, control for the DMA engine is also provided.
- CRC Calculation/Verification
- Data and Header CRC are automatically added for Outgoing Packets. CRCs are verified for incoming packets. Faulty packets are ignored. Additionally errors can be injected for TX packets (header and or data CRC).
- Ack Generation
- Acknowledge Packet Generation is based on incoming packet content, available buffer space as well as LLC state. As an added feature Acknowledges can be suppressed or erroneous Ack codes can be injected.
- Filtering
- NodeID (async) and channel number (iso) specific packet filter engine.
- Cycle Start Generation (optional)
- A Cycle Start Packet generation functionality with its associated Cycle_Time Register is optionally supported by the HW.
- ISO Ports (optional)
- Optionally, ISO Receive and/or ISO Transmit ports can be added. The purpose of these ports is to connect dedicated stream HW (e.g.: image/video generating/receiving HW) for the handling of data streams without burdening the host processor. Received and Transmitted isochronous packets can be routed through the ISO Ports therefore providing a dedicated and highly efficient data path for the isochronous packets. Optionally the packet headers will be skipped (RX) or automatically generated (TX).
- Monitor (optional)
- Optionally, a packet monitor is supported. This tool is mainly targeted for debugging purposes.
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