DDR1 DDR2 SDRAM Memory Controller

Features

• * Configurable number of chip select signals – two to four
• * Software programmable chip select address range for each chip select – 8MB to 4GB Compile time configurable memory data bus width. * Supports 16, 32 and 64 bits Utilization of write data mask signals for incomplete write bursts.
• * Configurable memory address bus width
• * Standard DDR-SDRAM control interface
• * External control signals for standard asynchronous static devices
• * Software configurable external memory device data width for each chip select
• * Supports 8, 16, 32 and 64 bits width for SDRAM devices and 8, 16 and 32 for asynchronous devices
• * Register interface for software initiated SDRAM initialization sequence
• * Support for asynchronous page mode static devices
• * Possible SDRAM burst sizes are 1, 2, 4 and 8
• * Software programmable asynchronous static memory device timing parameters for every chip select
• * Software programmable SDRAM memory device timing and organization
• * Additional DDR2 SDRAM control interface
• * Independent of data transmit and capture implementation
• * Pipelined, out-of-order memory command generation. Number of pipeline stages is selected at compile time according to application needs
• * Automatic SDRAM refresh generation
• * Register interface for software initialization and suspension of external memory devices

Deliverables

• * RTL Verilog source code
• * Verilog Test bench
• * Documentation
• * Example implementation
• * Hardware platform (optional)
• * Engineering Support